Precision, speed, low power, and size are attractive attributes of successive-approximation-register (SAR) analog-to-digital converters (ADCs). These features have made SAR ADCs popular with designers of data-acquisition modules, medical instruments, spectrum analyzers, process controls, scanners, and a myriad of other applications seeking cost-effective performance from precision data converters. But as these systems move up the performance ladder, they must satisfy the stringent market needs of even higher accuracy and increased throughput without sacrificing power dissipation or costing more.
Heeding this demand, mixed-signal designers at Analog Devices have crafted a 16-bit SAR ADC that sets a speed record of 1 Msample/s—double the 500-ksample/s rate available today. Without consuming very high current or stretching the die size, it breaks the speed barrier, but for a price. According to ADI's product manager Bhaskar Banerjee, the AD7671 will cost 50% more than the older AD7674.
"The AD7671 is unparalleled in precision and speed," asserts Michael Coln, senior design manager for ADI's Precision Nyquist Converter Group. "It's built to achieve speed without dissipating more power. The standard 0.6-µm double polysilicon CMOS process implemented ensures that it's small enough to fit inside of a miniature plastic package, thereby keeping its price tag lower." The AD7671 provides a pin-to-pin upgrade path for previous-generation SAR ADCs from Analog Devices. Like older members, it comes in a 48-lead low-profile quad flat pack (LQFP). The die measures 133 by 159 mils.
To achieve such high speed, ADI's designers had to overcome many hurdles, including designing a wideband comparator block. Applying engineering innovation to this circuit block let designers craft a novel comparator that helped accomplish the end goals. To support fast, 16-bit-accurate successive-approximation decisions, the patent-pending comparator implements a cascade of high-bandwidth preamplifier stages.
Internal details show that a four-stage preamplifier scheme provides the necessary gain-bandwidth product for the converter. The amplifiers, interconnected via a variety of switches, precede the latch (Fig. 1).
Using MOS transistors, the comparator block incorporates clever switching techniques for resetting as well as correcting the input and output offsets. For instance, to reset the preamplifier stages between the decisions and eliminate overload recovery times, the comparator includes output-zeroing (OZ) switches between the preamplifier stages. Individual preamplifier stages include input offset auto-zero (IZ) switches to curb the input voltage offset. The clock generator on-chip controls the switches.
Using an array equivalent to 16 binary weighted capacitors and an additional least-significant bit (LSB) capacitor, the converter employs capacitor charge redistribution (Fig. 2). The inverting input of the comparator is connected to dummy capacitors of the same value as the capacitive array, while the top plate of the capacitor array is attached to the noninverting input. Serving as a sampling capacitor, the array acquires the analog signal from the output of the resistive scaler. By switching each element of the capacitor array between reference ground and the reference, the comparator input is varied by binary weighted voltage steps. The Con-vert/Start signal initiates and completes the conversion cycle. It triggers the control logic, which, in turn, controls the switches.
The input structure has been modified from those of earlier members of this family. To permit both unipolar and bipolar input ranges, the ADC integrates a thin-film resistive network scaler at the input, allowing various input ranges. Unipolar ranges are 0 to 2.5 V, 0 to 5.0 V, and 0 to 10 V, while bipolar ranges are ±2.5 V, ±5 V, and ±10 V. The unit operates from a single 5-V supply, with a typical power dissipation of 150 mW at 1 Msample/s. Plus, it features a power-down mode, where consumption drops to a mere 7 µW maximum.
Because not all applications require fast throughput, the 16-bit ADC features three modes of operation. Power consumption varies according to speed—the slower the sampling, the lower the power dissipation. In the "warp" mode, the highest conversion speed of 1 Msample/s is possible. The conversion speed is 800 ksamples/s in the "normal" mode, and 666 ksamples/s in the "impulse" mode. Typical power consumption in the impulse mode varies with throughput at the rate of 150 µW/ksamples/s (Fig. 3).
Unlike the warp mode, the normal mode has no time limitation between conversions. In the warp mode, for instance, the full specified accuracy is only guaranteed when the time between conversions doesn't exceed 1 ms.
In addition to circuit im-provements, the AD7671 im-plements error-correction techniques and factory calibration to ensure high ac and dc performance at 16-bit resolution. Internal measurements reveal both impressive total-harmonic distortion (THD) and linearity. Tests prove that even at a 500-kHz Nyquist frequency, the ADC offers a THD of −87 dB. At 333 kHz, it's −92 dB. The signal-to-noise plus distortion (SINAD) ratio is 90 dB at 100 kHz.
Likewise, integral nonlinearity (INL) and differential nonlinearity (DNL) specifications, which define the accuracy of the ADC, are attractive. Although the maximum INL is guaranteed at 2.5 LSB with no missing 16-bit code, the real numbers are far better. When clocked at full speed, lab measurements indicate that INL performance is ±0.5 LSB. Similarly, DNL results show ±0.5 LSB with no missing codes.
The unit offers serial and parallel interface ports. While the parallel port accommodates 8- or 16-bit data widths, the two-wire serial interface and other digital I/O is compatible with both 3- and 5-V logic.
An on-chip, capacitor-array digital-to-analog converter also serves as the input track-and-hold amplifier, making it suitable for multiple multiplexed-channel applications. Other on-chip functions include a conversion clock, control logic, and calibration circuitry (Fig. 4).
Price & Availability
Sampling now, the AD7671 is slated to go into production later this year. Housed in a 48-lead LQFP, the 16-bit SAR ADC is specified for operation from −40°C to 85°C. In 10,000-piece quantities, each costs $25. Evaluation boards are available at $250 in single quantities.
Analog Devices Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106; (781) 329-4700; www.analog.com.