This idea was created to solve a design problem we faced a few months ago. The circuit we were working on was used to steer an H-bridge that was controlled by a TMS320F2810 digital signal processor (DSP).
During the final phase of the design, we discovered by chance that everything worked fine when the circuit was initially powered. However, if it was powered off for 5 to 15 seconds and then powered on again, the circuit started draining a lot of current through the H-bridge/load. This destabilized the power supply, and the DSP was kept in reset.
After some hardware and software debugging, we found that the problem was a steady high level on the pulse-width modulation (PWM) control lines when the TMS320F2810 was held in reset (power up). This DSP has internal pull-ups (20 to 80 k?) enabled on the uninitialized PWM outputs in order to maintain the pins at a known, defined level. Because the DSP-PWM pins are current limited to ±4 mA, they were interfaced to a MOSFET driver (LM5104) through a bootstrap capacitor to drive the H-bridge (Fig. 1).
This type of driver works very well, but the bootstrap capacitor should not be discharged completely (as in the case of a steady high level in pin 6). Although the MOSFET driver has an internal pull-down resistor attached to pin 6, its value is around 200 k?, which is much higher than the DSP pull-up. Because of that, the input level is held high when the system is in reset.
An additional pull-down resistor on pin 6 would have solved the problem, but at the cost of a higher current drain (the resistor value must be lower than the DSP pull-up) and longer low-to-high transitions. But the proposed solution (Fig. 2) guarantees that the output is high only for a defined period (depending on the values of RX, RPD, and CX) without affecting the PWM signal and with only a small increase in the power drain.
In this solution, CX defines the maximum high period and RX limits the transient current when the PWM signal is switching. RX and CX are determined by:
where:
VDSP is the DSP I/O supply,
IIO-LIM is the current limit for a DSP I/O pin,
TMAX is the maximum allowed pin 6 high time,
VTH is the threshold voltage of pin 6, and
RT = RPU + RX + RPD.
Assuming that CX is initially discharged and pin 6 is high, CX will be progressively charged through RPU, RX, and RPD. If PWM1 toggles to low in a time shorter than TMAX, CX will discharge fast through RX and D1 and the cycle starts again. But if PWM1 stays high longer than TMAX, the voltage on pin 6 will go under VTH and the LM5104 will switch the output to low.
Because of component tolerances, the calculation of TMAX is approximate. In practice, that poses no problem since controlled system evolution is far slower than the PWM control signal. One final tip: To limit the circuit EMI and prevent latch-up, the value of RX should be higher than that calculated by the formula.