Electronic Design

# Squeeze 10-Bit Performance From An 8-Bit ADC, Part 1: Additive Dithering

What’s the cost of an underused hardware resource? If you spec your microcontroller to have a 10-bit analog-to-digital converter (ADC) but only require 8 bits, you’ve paid for extra performance that just isn’t needed.

What’s the cost of an unused hardware resource? If you require 10-bit performance but only have an 8-bit ADC, your first inclination may be to add an external ADC to your system. The design becomes even more challenging when you’re designing a product that will require 8-bit performance for the standard model and 10 bits for the higher-end model.

As you’ll sell more standard models, you don’t want to burden your design with the extra cost of a higher-resolution ADC. And because of board-space limitations, adding an external ADC may not be acceptable. Fortunately, you can get 10-bit performance with an 8-bit ADC by averaging multiple samples. This process is called oversampling.

An ADC generates a digital output that’s proportional to the ratio of the input voltage to the input range. The resolution (Δ or least significant bit) is this range divided by the total number of possible steps. For example, an 8-bit ADC with a 2.048-V input range has a resolution of 8 mV (2.048 V/28 steps). Figure 1 illustrates the mapping of the analog input voltage versus the digital output, shown for a small section of this ADC.

For this ADC, the Δ is 8 mV and the output will be 0xc0 for an input of 1.536 V ±4 mV. 10-bit performance for the same input range requires a resolution of 2 mV. Getting 10-bit performance requires being able to resolve one-quarter steps.

Say you want to digitize 1.534 V to 10-bit resolution. The answer should be 767 counts (210 × 1.534 V/2.048 V) or 191.75 counts of the 8-bit ADC. Now suppose you have a digital-to-analog converter (DAC) that allows you to add a small amount of offset to the input. For instance, you can add four different values: –6, –3, +3, +6 mV.

The particular values aren’t important as long as they average to zero and have a peak-to-peak value greater than the ADC’s least significant bit, 8 mV in this case. These particular values do average to zero and have a peak-to-peak value of 12 mV. For each offset, the signal is digitized (Fig. 2).

The average of the four results is 191.75, and the sum is 767. This input has been digitized with 10-bit resolution. It takes four samples to calculate the result, or put differently, it has been “oversampled by four.” Adding a specific offset to the input to increase resolution by oversampling is known as additive “dithering” because it adds noise to your input and relies upon internal filtering to be removed. In this case, averaging the four signal removes it effectively.

This dither was generated with a hypothetical DAC. Although it could be done with a DAC, it would be an expensive solution. There are other ways to generate an acceptable dither. A triangle wave is a good choice for a dither as it has an even dispersion of values and averages out to zero. It is also quite easy to construct. If the triangle wave is correctly phased with the ADC, only four samples are required. Worst-case phasing would require eight samples.

When designing your system, you must decide if you want to oversample by four at the exact phase or oversample by eight and not worry about synchronization. This is a judgment call, but in my experience, systems that don’t require synchronization will be easier to implement. If there is acceptable ADC bandwidth, I would oversample by eight and avoid synchronization.

Next month, part 2 of this column will detail a practical way to implement triangular dither and use it to increase the resolution of an ADC from 8 to 10 bits.