Electronic Design

Squeeze 10-Bit Performance From An 8-Bit ADC, Part 2: Triangular Dithering

Part 1 of this column (ED Online 18899) showed how designers can use additive dither and oversampling to increase the resolution of an analog-to-digital converter (ADC). In this edition, we will illustrate a practical way to implement triangular dither.

Designers can generate a rail-to-rail triangle wave by XORing two square waves of different frequency and filtering the result (Fig. 1). When two square waves of the same frequency are XORed together, the output will always be low if they are in phase, high if they’re 180º out of phase, or some percentage high in proportion to the phase difference. This feature makes the XOR gate an inexpensive phase detector.

If square waves differ in frequency, they will continuously go from in phase to out of phase and back again. This cycle repeats at the difference of the two frequencies. If the proper filter is selected, the filtered output of two square waves of different frequencies is a rail-to-rail triangle wave with a frequency equal to the difference of the two frequencies.

Suppose you have an 8-bit, 10-ksample/s ADC with an input range of 2.048 V and an anti-aliasing, second-order, 3.3-kHz, low-pass filter connected to its input (Fig. 2). To make the design easier, the required dither isn’t going to be synchronized with the ADC, so an 8-sample design requires a dither frequency of 10 ksamples/s/8 samples or 1250 Hz.

It’s necessary to generate two frequencies that have a difference as close to 1250 Hz as possible while being large enough to be filtered by the anti-aliasing filter. Practical frequencies are limited by what system clocks you have available. Suppose for this example that 16 MHz is an available clock source.

One approach is to use 50% duty cycle pulse-width modulators (PWMs), one with a period of 224 counts and another with a period of 228 counts. They generate one square wave at 71.4428 kHz and another at 70.154 kHz for a difference of 1253 Hz. The logic supply from this example is 3.3 V, so the filtered triangle will have the same peak-to-peak amplitude.

The alias-aliasing filter is used to filter this pulse train. It’s nice that the filter gets to do double duty. The resistor that connects to the filter is sized to reduce the amplitude to 23 mV p-p (3.3 V times 3.40k/474k) or 23 mV p-p. This is well above the least-significant bit (LSB) value of 8 mV. The 3.3-kHz filter will effectively remove the 70-kHz component of the PWM signals.

A capacitor is placed in series with this new resistor to make a high pass filter that blocks the dc half of the dither. For this example, a 0.01-µF capacitor was chosen, resulting in a high pass value of 1/2πRC or 33 Hz. This is well below the dither frequency and will block out the dc component. All that is left to do is accumulate eight ADC samples, shift the data right one bit, and you have 10-bit resolution.

It isn’t always necessary to add dither. Sometimes a system dithers itself. Part 3 will show when it is possible to exploit this feature.

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