Electronic Design

Synchronous Detection Plays A Role In Better Analog Design

Designers can use this technique to exploit delta-sigma modulation and density-domain signal processing for better performance.

Synchronous detection is a measurement method where a stimulus is modulated with some frequency and the response is demodulated to bring the signal back down to base band. Performed when a dc stimulus is not acceptable, it’s widely used in medical and scientific signal conditioning and in capacitive, inductive, or complex impedance measurements. It also allows for the collection of signals in a high-noise environment. Densitydomain signal processing permits inexpensive demodulation, while the averaging of analog-to-digital converters (ADCs) enables inexpensive filtering, resulting in a very cost-effective implementation.

Although generally seen as a method of AM radio demodulation, synchronous detection is used in test systems to make measurements in some specific narrow frequency band. A synchronous detector consists of a reference value mixed (multiplied) with a specific modulation frequency to generate a modulated stimulus signal that is fed to the system under test (SUT) (Fig. 1). The SUT output is again mixed with the same modulation frequency. This mixing causes response bandwidth to be shifted to around dc and twice the modulation frequency. A low-pass filter is used to remove the higher-frequency components, leaving a demodulated response.

If the SUT is a linear system, its response will be a sinusoid with some amplitude VP and some phase delay . Multiplying this output by the modulation signal and also with another reference signal, 90° out of phase, results in Equation 1. The product of two sinusoids yields the average of two sinusoids, one being the lower frequency difference of the two terms while the other is the higher frequency sum. When it is low-pass filtered, the high-frequency component is removed, leaving only what is shown in Equation 2.

The square root of the sum of these signals squared produces the signal amplitude. Taking the arctangent of the two produces the phase. This is a very straightforward and standard technique for synchronously detecting signals. Its biggest limitation is that it requires two four-quadrant analog multipliers.

An alterative method is to use polarity modulators. A polarity modulator has a digital modulating input that flips the signal polarity either positive or negative. It’s used to chop a reference voltage (Fig. 2). This signal is then bandpass filtered to produce a sinusoid of specific amplitude and frequency. It’s in phase with the modulating square wave used to generate it. This is the modulated stimulus, and it is fed to the SUT. The SUT output is again modulated. By exploiting the averaging effect of an integrating ADC, the low-pass filter can be removed.

To guarantee complete averaging, the integration time of the ADC must be set to be an integer number of modulator cycles. Fortunately, with a complete system- on-a-chip (SoC), this constraint is easily satisfied. Figure 3 shows the demodulation of a response signal with a 22.5° phase delay.

The top waveform is the response with a 22.5° phase delay. The middle waveform is the response signal modulated with the reference square wave. Its average is 59% of the peak. The bottom waveform is the response signal modulated with the reference square wave shifted by 90°. Its average is 24% of the peak. The arctangent of the ratio of these two averages is 22.5°. Note that the modulated waveform repeats every half cycle. Equation 3 shows the average for a response with a peak amplitude of VP and a phase delay of .

With these two equations, it’s possible to isolate the peak voltage and the phase delay of a response signal. Although polarity modulators reduce the cost of synchronous detection, the use of delta-sigma modulation and density-domain signal processing can even further reduce the cost.

The density domain allows an analog value to be represented as a digital stream, where logic high represents a positive reference value and logic 0 represents a negative reference value. Density is defined as the percentage of the waveform that is positive. The actual waveform is not important. What matters is the density. Equation 4 shows the relationship between the analog value, reference, and density values. Equation 5 defines the density, given the analog and reference values. With logic high defined as positive and logic low defined as negative, an XNOR gate acts as a density multiplier for two uncorrelated density inputs. Given two analog signals (A1, A2) and their corresponding density values (d1, d2), Equation 6 shows the density output of these XNORed densities.

Substituting this value into Equation 4 provides the new analog value as a function of these two densities (Equation 7). Substituting the density with the analog value defined in Equation 5 into Equation 7 produces the new analog value as a function of the input analog values (Equation 8).

In the density domain, multiplication is performed with an XNOR gate. The delta-sigma modulator (?SM), which converts an analog input into a digital density output, is commonly coupled with a decimating digital filter to make an ADC. However, the output stream can be mixed digitally to perform a polarity modulation. Figure 4 shows the density output of a ?SM for a sinusoidal analog input.

The top digital stream is the ?SM density output. Note that it is mostly logichigh when the input is at its peak and mostly logiclow for minimum signal. The middle digital stream is the density signal XNORed with the square wave used to make the sinusoid. They are in phase. Note that the output is now high for both the most positive and negative signal amplitudes. The lower logic stream is the density output mixed with a square wave 90° out of phase. Figure 5 shows data with the same setup, only the oscilloscope is set in an averaging mode. This acts as a crude filter on the three logic streams.

The top logic stream is reconstructed back to a sinusoid. The middle logic stream is reconstructed to the absolute value of the sinusoid. The lower logic steam is polarity-modulated 90° out of phase. If these two outputs are fed to an integrating ADC that averages for an integer number of cycles, the in-phase result is 2 VP/p, while the one output, 90° out of phase, is zero. Figure 6 shows the more simplified synchronous detector.

We’ll illustrate an implantation of these concepts using an impedence meter with a synchronous detector (Fig. 7). This topology has particular advantages that become apparent in Equation 9. Taking the difference of two readings removes any offset error, while the ratio of these differences removes any gain error. The accuracy of the reference resister limits the accuracy of the impedance measurement.

This particular design is implemented with a Cypress CY8C27443 programmable SoC on a CY3210 PSoC evaluation board. The stimulus signal is a square wave set at 7.8125 kHz. Setting the two pulse-width modulators (PWMs) to have a clock of 1 MHz, a 50% duty, and a period of 128 achieves this square wave (Fig. 8).

To guarantee the correct phasing of the two PWMs, both are enabled with an output row (RO0\\[3\\]) digital lookup table (LUT). These two PWMs are sequentially started in software but don’t actually start operating until enabled by the LUT to be logic-high in software. These PWM outputs are connected to two adjacent output rows (RO0\\[0\\], RO0\\[1\\]). The RO0\\[0\\] LUT is used to route one of these signals to an output pin (P0.0). This is the signal used to modulate the unit under test (UUT) response. The in-phase PWM is also connected to the broadcast row (BC0), allowing it to be used to control the band-pass filter’s built-in polarity modulator.

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The analog section contains a band-pass filter designed with a center frequency of 7.8125 kHz and a Q of four. Its output is a 7.8125-kHz sinusoid with an amplitude of 1.15 V and a phase delay of zero. It is connected to the analog output buffer on P0.5. This is the modulated stimulus.

The ADC is set for 14 bits and uses a 4-MHz column clock. This sets the integration time to 16.38 ms or exactly 128 cycles of 7.8125 kHz. The analog part of the ADC is a ?SM. The column 0 analog comparator LUT is set to be an XNOR to modulate this ?SM density stream. A comparator is required to get the modulation signal from P0.0 to the column 1 comparator bus. A buffer is used to connect the input signal MUX to the ADC input. Software is used to connect AGND to the analog output buffer on P0.3

For all tests, the reference resister used was measured and found to be 10.02 kO. A Fluke 85 multimeter performed the measurement. For the first impedance test, a 15-kO resistor was measured. The following data was collected for each of the three inputs (in counts):

VHIGH = 4568 – i401 counts
VMID = 2742 – i227 counts
VLOW = 0 + i1 counts

Although this is a purely resistive measurement, there is a slightly out-ofphase component. This is because of delay in the analog path. In a production unit, the phase of the modulation waveforms would be adjusted to compensate for this. Applying this data to Equation 9 results in Equation 10.

This works out to an amplitude of 15.03 kO and a phase shift of 0.6°. When measured with a Fluke 85 multimeter, the test resister value is measured at 14.99 kO. For the second impedance test, a 1000-pF capacitor is measured. The following data is collected for each of the three inputs:

VHIGH = 4588 – i407 counts
VMID = 3812 + i1488 counts
VLOW = –1 – i2 counts

Applying this data to Equation 9 results in Equation 11. This works out to an amplitude of 20.02 kO and 89° phase shift. Equation 12 shows the capacitance value.

Delta-sigma modulation easily allows analog signals to be converted to the density domain. Density-domain signal processing and averaging ADCs allow for the inexpensive construction of synchronous detectors in particular and signal multipliers in general.

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