Without the development of standard-cell libraries and, subsequently, logic synthesis in the 1980s, the design of today's multimillion-gate SoCs and ASICs would be problematic, if not outright impossible. Synthesis of combinatorial digital logic from an abstract representation (register-transfer level, or RTL) to its physical equivalent in the form of a gate-level schematic brought about a paradigm shift in productivity for digital logic designers.
But analog and mixed-signal content on SoCs is quickly rising. At least one forecast expects almost 70% of all IC designs to have analog or mixed-signal content by 2006. A number of factors are driving this increase in analog content, including the shift in emphasis by the electronics industry away from computing, toward communications, consumer, and automotive markets. All of these markets demand more analog and mixed-signal processing than the computing market (Fig. 1).
The advent of ever-faster digital circuitry and advanced fabrication processes themselves cause what some call "digital becoming analog." Even "pure" digital ICs contain I/O drivers that pump away at furious speeds. Clock nets require deskewing with analog phase-locked loops (PLLs) to meet timing requirements. These analog design problems require analog blocks to solve them, and they occur more often as time passes.
A pool of talent that's not growing must contend with all of this analog and mixed-signal design. Plus, as more mixed-signal blocks come into play, some of this analog design work is being shoveled over to the digital designers. Now they must really face that there are signal transitions that fall between one and zero.
So beleaguered analog designers await a paradigm shift in their design methodology paralleling that which occurred for the digital designer in the form of logic synthesis (Fig. 2). Unfortunately, it hasn't quite arrived yet. Some strongly doubt it ever will. But the good news is that pieces of the puzzle are emerging. While it's unclear if there will ever be a synthesis tool like Synopsys' Design Compiler for the analog/mixed-signal world, there's certainly a lot of room for more automation in analog.
Several factors mitigate against a pushbutton style of synthesis for analog in which a designer would feed a high-level functional or behavioral description of his or her circuit into a tool and receive a transistor-level netlist and schematic. One is the inherently full-custom nature of analog design.
"From an algorithmic point of view, the analog synthesis problem is a very difficult one," says Amit Gupta, vice president of business development at Analog Design Automation (ADA). Because so many more parametric tradeoffs must be made in analog circuitry, the number of possible combinations for circuit elements is enormous. "Because the computer power isn't there, you need the algorithms to efficiently sift through that vast search space," Gupta says.
The complexity of analog design as a barrier to a real synthesis technology leads directly to another key stumbling block in methodology development—the analog designers themselves. "Analog designers don't want to move up the hierarchy chain because they want to optimize at the lowest level," says James Spoto, president and CEO of Applied Wave Research.
Much analog design work is done at the transistor level, but even that low level isn't enough for some designers. "If you just model a CMOS transistor with a certain size, that's not good enough for an analog designer," explains Coby Zelnik, Sagantec's senior vice president of business development. "They have to see exactly how it looks, the layout, and many other details that wouldn't make any difference to a digital designer."
Those who would entice the analog designers to move up in abstraction are quite aware of the difficulty in getting them to abandon their tried-and-true handcrafted methodologies. With all of their dogged insistence on retaining full-custom control over their designs, will analog designers even want a pushbutton synthesis tool that makes their decisions for them?
The answer, says Steve Lewis, product marketing manager for analog/mixed-signal products at Cadence Design Systems, is yes and no. According to Lewis, when facing EDA vendors, analog designers tend to be grumpy. But they use EDA tools and really can't complete their jobs without them. There's a fine line, though, between improving their productivity and keeping them firmly in charge of their own designs.
Today's "analog synthesis" tools don't even begin to approach a Design Compiler's ability to go directly from RTL to gates. Most existing capabilities concentrate on synthesis of well-defined, easily parameterized structures. Examples include filters or operational amplifiers. But can that be broadened to include other types of analog circuits?
When considering the future of synthesis in the analog/mixed-signal world, one must consider the limitations that intellectual property (IP) libraries impose. "When starting out with a behavioral or high-level definition of what you want the analog portion of your circuit to do, you need to be able to create and modify structures as opposed to drawing from a predefined library where you're picking topologies or IP," says ADA's Gupta.
One could point to the development of standard-cell libraries as the key technology development that made logic synthesis possible. There's a significant difference between digital IP and analog IP, though, that makes things much more complicated in the analog world.
Digital building blocks and standard cells are considerably simpler than analog blocks. For example, they can be fixed NAND or NOR gates with associated finite delays. Analog, however, is a continuous world in which blocks must vary over a range of specifications and parameters. "That's why you haven't seen analog cell libraries be effective, because they've been fixed," says AWR's Spoto. In addition to variable behavior, analog library elements are much more sensitive to process variables than are digital elements.
The notion of moving up in abstraction and starting from a behavioral description of an analog block is where some existing EDA tools for analog diverge. Some methodologies assume that the chief analog designer, a senior engineer with many years of experience, begins the process of designing a functional block with a circuit and topology already in mind.
"In analog design today, the master designer guesses at a schematic, transistor sizes, and a topology," says Peter Santos, vice president of marketing and business development at Barcelona Design. Then, he says, Spice is run on the circuit, not to confirm that the design is viable, but rather as part of the design process.
After analyzing the results of the Spice run, the designer makes changes to transistor widths and lengths, and to the topology, then repeats the process. Iterations continue until the designer feels close to a usable result in terms of the block's functional specification. Finally, one last Spice simulation serves as a verification run.
This approach is time-consuming, and the quality of results is highly dependent on the designer's experience. Barcelona's equation-based approach to IP creation works the other way around. Here, the designer begins with a set of ideal specifications that are input into a set of equations. Likewise, because so many analog circuits are implemented on digital processes, a second set of equations is used to account for process parameters. Using a technique called geometric programming, the tool's solver produces a set of transistor sizings, and placement and routing for the block as a whole.
But once again, we must return to the particular nature of the analog designer. While an EDA tool like Barcelona's product might deliver an optimized set of transistor sizings, and even place and route them, the analog designers are unlikely to stop there and accept what the tool gives them at face value. The output of such a tool can be considered as a starting point because it accomplishes part of the task for the designer.
Another approach, in terms of methodology, is represented by ADA's Genius product family. ADA's president and CEO, Matthew Raggett, says tools that hew more closely to the analog designer's preferred methodology are apt to be less objectionable than those that try to take them out of the process.
The Genius tools work from a circuit topology, as the analog designer is wont to do, and produce a range of results that are optimized across the parametric tradeoff curve. Thus, they let the designers retain a high degree of control. Designers can choose the one that best suits their needs from a number of optimized transistor-level netlists (Fig. 3).
Another aspect of the Genius meth-odology is that it fits completely into the designer's environment. It uses the customer's simulator, fab models, and testbenches to measure the metrics or specifications of the circuit. "As a result, because we're designing based on feedback from a user's simulator, the user can resimulate an output from our system with his or her simulator and confirm the results," Gupta says. "That's important for adoption in that we're not trying to model the system or circuit in terms of an equation. It's an important aspect of gaining trust."
Moving up in abstraction in analog design implies the use of a high-level design language, such as Verilog-A or Verilog-A/M-S. Work on analog languages is being coordinated under the umbrella of the Accellera consortium. A top-down methodology starting from a higher level of abstraction is becoming more common in system-level architecture development. But it's still a subject for "evangelization" among analog designers. "Customers say 'prove it' when we suggest that using design languages improves simulation speed or enables simulations that they couldn't do before," says Cadence's Lewis.
Certain classes of blocks lend themselves to modeling on the behavioral level. As noted earlier, they generally have well-defined topologies like PLLs, which are known to be a bear to simulate at the transistor level. "We've been able to devise methodologies for modeling the voltage-controlled oscillator, some filtering, and improve speed from 20× to 100× with reasonable accuracy within 3% to 4%," Lewis says. The goal is to use the behavioral PLL model and blend it in simulation with the rest of the digital circuit that it's used to control.
Key to making behavioral models accurate is knowing how best to write them in the high-level language. Designers must come to grips with which parameters really need to be modeled and which don't. Otherwise, you could conceivably build a behavioral model that simulates more slowly than its transistor-level counterpart.
According to Aykut Dengi, design flow development manager at Neolinear, behavioral models will inevitably play a role in analog. "Currently, there are no really good standards for them," he says. Dengi sees designers using proprietary in-house models written in their language of preference. "I've seen MatLab models, Verilog-A models, and models that are actually based on Spice elements," Dengi says. "The maturity of that area is improving very fast, but right now, it's not there for mainstream use, and it has to get there for analog synthesis to play a bigger role."
An easy generalization would be to say that the hard-core analog designer will want to build a transistor-level model first, then bring that up to a behavioral level. Dengi sees a mixture of the two approaches in use. "A bottom-up approach is more suitable for companies that build their own analog parts and reuse them extensively," he says. But in practical reality, elements of both top-down and bottom-up approaches to model creation come into play.
Say a designer is building an RF receiver. Starting from overall specifications, the first step might be to juggle some behavioral models of the circuit blocks in MatLab. Next, more detailed specifications are developed for each block and the blocks are farmed out to design groups for schematic creation. Those schematics are translated back up into the behavioral level for system-level simulation, after which there may be tradeoffs between various parameters, such as gain and noise, among others.
According to Howard Tang, senior analog IC designer at NurLogic Design, a top-down analog design methodology implementing behavioral models makes the process of working out interaction between blocks much faster and easier. Early simulations are carried out via models written in Verilog-A, or another high-level analog language, to see how the blocks interact.
The next step is to replace particular blocks with transistor-level models, while leaving everything else the same. "This would work better for a large chip project," says Tang. "For a simple block, such as an op amp or PLL, it's not really advisable. You have too many things to model. But for a large mixed-signal chip, it's a good idea."
Other aspects of analog design have also improved in productivity. Once a design has been moved down to a physical implementation, it's often necessary to reimplement that design on a different or more advanced process technology. For instance, Sagantec's SiClone tool can translate an existing layout to a new set of design rules, saving designers from the task of completely redesigning to the new process.
But in the synthesis arena itself, a large window of opportunity remains open to EDA tool vendors. "I don't see anything on the near horizon to match what Design Compiler does for the digital world," says Cadence's Steve Lewis. "People will approach analog synthesis from the known topologies and structures as a starting point. The analog languages and, ultimately, mixed-signal languages need some time to brew, and people need to get their hands around them." Analog designers will continue toiling at the transistor level until the sheer complexity of their designs compels them to move up in abstraction.
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Analog Design Automation Inc.
Applied Wave Research Inc.
Cadence Design Systems
Nurlogic Designs Inc.
Sagantec North America