The burgeoning digital communications market has generated an unprecedented demand for a new generation of high-speed digital-to-analog converters (DACs). Many of these converters are being used in the transmit signal path to reconstruct the complex analog waveforms demanded by sophisticated digital modulation schemes. Advances in very-large-scale integration (VLSI) and digital-signal processing (DSP) technology now allow for more of the signal processing to be performed in the digital domain. There are many reasons behind the digital shift: higher spectral efficiency and capacity, improved quality, added services, software programmability, and lower power.
Synthesizing communication signals in the digital domain typically allows the characteristics of a signal to be precisely controlled, if not predicted. However, in the reconstruction process of a digitally synthesized signal, it's the DAC and its nonideal characteristics that often yields unpredictable results. In some cases, it's the performance of the DACs that actually determines whether a particular modulation scheme or system architecture can be implemented.
Unlike high-speed video DACs used to recreate images on high-resolution PC and workstation monitors, the performance of these converters are often analyzed in the frequency domain with secondary consideration to time domain and dc specifications. Selecting the optimum DAC for a given application requires an understanding of how to interpret various converter specifications and their effects on system performance. In addition, achieving the optimum performance while realizing other system objectives demands careful attention to various analog- and digital- interface issues (to be covered in Part II of this article).
Responding to the needs of these emerging markets, semiconductor vendors are releasing a new generation of CMOS and bipolar DACs that range from standard products of varying resolution, speed, and performance to more integrated products incorporating various DSP functions. These DSP functions may include digital interpolation filters, which reduce the complexity and cost of the required analog reconstruction filter, or complete application-specific digital modulators for quadrature or spread-spectrum modulation schemes.
Better Performance Much design effort has gone into improving the frequency-domain (ac) and static (dc) performance of these devices, while meeting other system objectives such as single-supply operation, lower power consumption, lower cost, and ease of digital integration. Several semiconductor vendors have elected to focus their effort on designing high-performance DACs using a digital CMOS process. In fact, today's CMOS DACs have overcome many of the deficiencies associated with their predecessors, video DACs, and now provide performance that's comparable, if not superior, to their bipolar or BiCMOS counterparts. As a result, system engineers are wise to keep informed about the latest trends and product releases that can affect how designers craft a next-generation system.This renewed interest in high-speed DACs also has highlighted many shortcomings in the way these critical devices are traditionally described. As many engineers are learning through painful experience, selecting a DAC for any waveform- reconstruction application purely based on resolution, settling time, dc accuracy, and glitch impulse can often provide results far worse than anticipated.
Although certain observations can be made about the effects that the static (dc) and dynamic (time domain) specifications may have on a DAC's frequency (ac linearity) performance, the cumulative effect still remains impossible to predict, which is why simulation models do not currently exist. Because both static and dynamic nonlinearities will manifest themselves in the frequency domain, and contribute to a DAC's large- and small-signal distortion performance, a high-speed DAC should be primarily evaluated using specifications and characterization data pertaining to its frequency domain.
The frequency-domain performance of high-speed DACs has traditionally been characterized by analyzing the spectral output of reconstructed single-tone sine waves (Fig. 1). Single-tone sine-wave characterization of any analog or mixed-signal component allows for the easy identification of its various nonlinearities. Until recently, most of this analysis was performed using only full-scale (in other words, 0 dBFS) sine waves at a few selected update rates, presenting limited insight into a DAC's performance in a real-world communications application.
The spectral output of a DAC will contain both harmonic (including aliased harmonics) and nonharmonic spurious components that weren't part of the original digitally synthesized sine wave. Figure 1 represents a single measurement point in which the DAC's amplitude, output frequency, update rate, and operating conditions are all uniquely specified. Changing any of these conditions will often modify the nature of these spurious components. Consequently, multiple measurement points using different synthesized waveforms with varying DAC operating conditions must be taken, analyzed, and plotted to accurately ascertain a DAC's performance. All of this activity must be done while capturing any significant performance trends. To ease the selection process, the datasheets of more recently released converters will contain several pages of characterization curves.
Dynamic Range Spurious-free dynamic range (SFDR), perhaps the most-often-quoted DAC specification, defines the difference, in decibels, between the rms power of the fundamental and the largest spurious signal within a specified band. SFDR is usually specified over the full Nyquist region extending from dc to one-half the data-update rate (fCLOCK/2).Typically, the worst spur is harmonically related and constitutes more than 80% of the total harmonic energy. Therefore, total harmonic distortion (THD) is rarely plotted over frequency because it's often only 1- to 3-dB worse than the SFDR performance. However, THD characterization curves plotting the three most significant distortion components can sometimes be helpful in determining which specific nonlinearity(ies) (such as second- or third-order distortion) limits a DAC's performance. Then, the effects of that nonlinearity can possibly be avoided via careful placement of the reconstructed signal.
SFDR also can be specified over a narrowband or window that purposely excludes the worst spur. The usefulness of this particular specification is relegated to those narrowband applications (for example, clock generation using direct digital synthesis) in which the DAC's full-scale output is operated over a limited spectral region, with the notion that the dominant "out-of-band" spurs can be filtered. In these applications, generating signals that are centered at either one-quarter or one-third the DAC's update rate will typically provide the worst-case performance due to the aliasing-back effect of the DAC's second or third harmonic. Thus, it may need to be avoided.
Signal-To-Noise Ratio A DAC's noise performance also is becoming increasingly important in determining its suitability in various communication applications (such as spread spectrum). In these applications, the carrier-to-noise ratio (CNR) of the reconstructed waveform that includes the effects of both noise and distortion will directly affect the system's bit-error rate (BER). Although the effects of quantization (representation of an analog waveform with a digital word of finite resolution) on a DAC's noise performance can be easily predicted, the additive noise effects resulting from differential nonlinearity (DNL), digital feedthrough, and jitter are more difficult to predict.Specifications and characterization curves that reveal the signal-to-noise ratio performance with and without distortion (SNR and SINAD) are beginning to appear on the datasheets of 8- and 10- bit DACs. For converters with 12-bit or higher resolution, the accurate characterization and testing of these important performance parameters becomes much more challenging.
As previously mentioned, full-scale sine-wave characterization data is useful, but is often still insufficient in representing a DAC's performance in a real-world communications application. The characteristics of the reconstructed multitone (carrier), spread spectrum, or QAM waveform are far different than a simple, full-scale sine wave. In fact, a DAC's spectral performance in a full-scale, single-tone waveform at the highest specified frequency (fH) of a band-limited waveform is typically indicative of a DAC's worst-case performance for that given waveform. In the time domain, this full-scale sine wave represents the lowest peak-to-rms ratio or crest factor (VPEAK/VRMS) that this band-limited signal will encounter.
However, the inherent nature of a multitone, spread spectrum, or QAM waveform in which the spectral energy of the waveform is spread over a designated bandwidth will result in a higher peak-to-rms ratio when compared to the case of a simple, full-scale sine wave. As the reconstructed waveform's peak-to-average ratio increases, an increasing amount of the signal energy is concentrated around the DAC's midscale value. As a result, a DAC's small-scale dynamic and static linearity become increasingly more critical in obtaining low intermodulation distortion and maintaining sufficient carrier-to-noise ratios for a given modulation scheme. Hence, the systems engineer also must keep in mind the nature of the specific signal to be synthesized, and determine which DAC specifications and set of characterization data has the most relevance in their communications design.
An example of a band-limited multitone vector shows eight tones centered around one-half the Nyquist bandwidth, fCLOCK/4. This particular multitone vector has a peak-to-rms ratio of 13.5 dB compared to a sine wave's peak-to-rms ratio of 3 dB. A snapshot of this reconstructed multitone vector in the time domain reveals the higher signal content around the midscale value.
A DAC's small-scale linearity performance also is an important consideration in applications where additive dynamic range is required for gain control or predistortion signal conditioning. For instance, a DAC with sufficient dynamic range can be used to provide additional gain control of its reconstructed signal. In fact, the gain can be controlled in 6 dB increments by simply performing a shift left or right on the DAC's digital input word.
Intentional Predistortion Other applications may intentionally predistort a DAC's digital input signal to compensate for nonlinearities associated with the subsequent analog components in the signal chain. For example, the signal compression associated with a power amplifier can be compensated for by predistorting the DAC's digital input with the inverse nonlinear-transfer function of the power amplifier. In either case, the DAC's performance at reduced signal levels should be carefully evaluated.Characterization curves revealing a DAC's single-tone SFDR performance at different fixed update rates as both the output frequency and amplitude are swept, are useful for many communication applications because the DAC update rate is often fixed by design (Fig. 3). Such a set of curves for the AD9762, a 12-bit member of Analog Devices CMOS TxDAC family, are shown in which the SFDR is measured relative to the single tone (-dBc) as opposed to its full-scale value (dBFS).
A more informative DAC datasheet will present several of these characterization curves at different sample rates (for example, 5, 25, 50, 100, and 125 Msamples/s) because high-speed DACs are often operated over a myriad of sample rates below their maximum specified rate. Note how the full-scale single-tone curve exhibits the fastest roll-off in SFDR performance as the frequency increases. This change is indicative of how quickly dynamic nonlinearities such as code-dependent glitch, slewing, and settling characteristics prevail over the static nonlinearities such as integral linearity.
Perhaps equally intriguing is that the lower-level signals of -6 and -12 dBFS provide superior SFDR performance over a larger span of output frequencies. The performance levels suggest that operating some DACs with less than full-scale signals can actually be advantageous in meeting a particular system's SFDR requirements. In other words, for applications that require full-scale SFDR performance above 65 dBc over their full bandwidths, but yet only need 10-bits of resolution, a designer may want to consider selecting a 12-bit DAC, and use only one-half or one-quarter of its dynamic range.
Small-Scale Linearity Maintaining decent small-scale linearity across the full span of a DAC's transfer function is essential to maintaining excellent multitone performance. Although characterizing a DAC's multitone performance tends to be application specific, much insight into the potential performance of a DAC also can be gained by evaluating its swept-power (amplitude) performance for single, dual, and multitone test vectors at different clock rates and carrier frequencies. The DAC is evaluated at different clock rates when reconstructing a specific waveform whose amplitude is decreased in 3-dB increments from full-scale (0 dBFS). For each specific waveform, a graph showing the SFDR (over Nyquist) performance versus amplitude can be generated at the different tested clock rates with the carriers-to-clock ratio remaining constant.Analysis of a DAC's swept-amplitude-SFDR results can often lead to some surprising revelations that may at first appear counter intuitive. For instance, in comparing the SFDR-versus-amplitude performance between the AD9762, the 12-bit CMOS DAC, and a recently released 14-bit BiCMOS DAC, the BiCMOS has an advantage in resolution, settling time, dc accuracy, and glitch energy over the lower cost and lower power CMOS DAC (Fig. 4). This comparison is based on the static linearity and dynamic specifications stated in each datasheet.
Both DACs were updated at 25 and 100 Msamples/s while reconstructing an output frequency of 5 and 20 MHz. In this case, the SFDR is plotted relative to a full-scale output to underscore how the SFDR performance of the AD9762 actually improves as the amplitude is reduced. In the meantime, the 14-bit BiCMOS performance remains relatively unchanged. At both 25 and 100 Msamples/s, the AD9762 begins to display superior SFDR performance for single-tones below -4 dBFS. For reconstructed amplitudes below -9 dBFS, the difference in SFDR performance between the AD9762 and the BiCMOS DAC can be as great as 10 to 15 dB, proving a DAC's resolution, static linearity, and dynamic specifications don't necessarily guarantee dynamic range! Multitone tests performed at similar update rates and output frequencies reveal that the AD9762 consistently shows better SFDR and intermodulation distortion performance.
A multitone test vector may consist of several equal amplitude, equally spaced carriers that are each representative of a channel within a defined bandwidth. In many cases, one or more tones are removed such that the intermodulation distortion performance of the DAC can be evaluated. Nonlinearities associated with the DAC will create spurious tones of which some may fall back into the "empty" channel, limiting a channel's carrier-to-noise ratio.
In the case of multichannel (FDMA) communications applications such as cellular phone or cable television systems, this undesirable spur is often referred to as an "interferer." Other spurious components falling outside the band of interest also may be important, depending on the system's spectral mask and filtering requirements. Regardless, regulatory or standards bodies such as the FCC have placed strict limits on the amount of out-of-band noise and distortion a transmitter can generate.
The particular test vector was centered around one-half the Nyquist bandwidth (fCLOCK/4) with a passband of fCLOCK/10. Centering the tones at a much lower region (fCLOCK/10) typically leads to an improvement in performance, while centering the tones at a higher region (fCLOCK/2.5) often results in a degradation in performance. In assessing a DAC's multitone performance, it also is recommended that several devices be tested under the same exact conditions to determine any performance variability among devices.