Multichannel television sound (MTS), better known as Broadcast Television System Committee (BTSC) encoding, is used in many analog cable set-top boxes for TV. The BTSC pilot is at the same frequency (15.734 kHz) as the horizontal video sync. The pilot signal is used to recover the L-R, SAP, and PRO audio channels. And by applying the principles of phase-locked loops (PLLs) and closed-loop feedback in a novel manner, it can generate the stable, high-speed master clock required to encode the video signal.
This article illustrates how a dual-channel BTSC encoder can generate a phased-locked master clock. One channel is used to generate an audio pilot tone, and the second is used for the stereo-encoded output. The output frequency, fMCLK, is typically known. The goal, then, is to set the divider in a PLL frequency synthesizer so that fMCLK is a multiple of an input reference, such as the horizontal sync frequency, fH-SYNC, of NTSC video (Fig. 1).
However, if an IC that requires fMCLK is incorporated into the feedback loop, the phase detector would follow the errors more closely, since any errors in fMCLK of the IC will be reflected immediately to the phase-detector output. Of course, until the loop settles, fMCLK is an unknown. This unconventional method, though, will provide an accurate master clock to the IC in the feedback loop as long as a suitable IC is chosen.
To derive a high-speed MCLK using the PLL frequency synthesizer concept, an AD71028 dual-channel BTSC encoder and a comparator serve in place of the N divider in the feedback loop. The stereo encoder adds a dbx-encoded, noise-reduced stereo subchannel (L-R) to the main monaural channel (L+R). A BTSC pilot tone, used by audio/video receivers to recover the L-R signal, is added to the output of the encoder.
This pilot tone will track the horizontal sync rate when the loop has settled, so fMCLK must be precisely 12.288 MHz for the pilot tone to be 15.734 kHz. When the PLL has not yet settled, fMCLK will be an irrational multiple of the instantaneous frequency of the BTSC encoder output, fBTSC_OUT (i.e., MCLK = a • fBTSC_OUT). In other words, when the loop doesn't lock, both fMCLK and the fBTSC_OUT will move until the error at the phase detector output is nearly eliminated.In this application, the PLL concept works because the AD71028 core generates the pilot tone digitally at a fixed fractional ratio of fMCLK. The PLL-produced MCLK is shown in Figure 2. The comparator following the decoder provides a square-wave pilot signal to the phase detector. The BTSC's second channel can be used to provide the audio signal in the A/V receiver.
