First, to those of you who have sent me e-mails about my delta-sigma series, thank you. I appreciate the kind words and notification of errors. I also received a few e-mails from some readers, mostly grad students, wanting to let me know they are way smarter than me.
They included questions guaranteed to confirm their position— for example, what effect does first- through third-stage parasitic capacitance have on overall differential non-linearity performance in a third-order modulator? It sort of breaks their spirit when I admit they are most likely smarter than me and I offer to send them a certificate publicly stating so.
In this edition, we’ll explore density signal processing (DSM), a concept that may be new to many of you. DSM is interesting because it enables you to shift signal processing from a microcontroller or DSP and implement it in less expensive logic gates.
THE ANALOG HALF
A delta-sigma modulator (?S?) is generally seen as the analog half of an analog-to-digital converter (ADC). It converts an analog input into a digital output stream. By knowing the percentage of the logic stream that’s high as well as the values of the references, it’s possible to determine what that input signal must have been.
For a lack of a better term, let’s call this percentage “density.” The second half of an ADC is a digital filter that measures this density and converts it into a digital word. The relationship between an analog signal (AX) and its density (dX) given bipolar references (±Ref) is:
The nice thing about expressing a value as a logic stream is that reconstruction resolution depends on how long you look at it. Running it for 100 clocks should allow resolution of one part in 100. Running it for 10,000 cycles should allow resolution of one part in 10,000. The analog value has been converted to a logic stream. Again for a lack of better terms I refer to this as conversion to the density domain.
A ?S? can be much more than just the analog half of an ADC. It is a fundamental building block of mixed-signal design, as fundamental as the D flip-flop. Most engineers treat a D flip-flop as a black box with particular specifications such as setup time, hold time, and delay time. Only flip-flop designers have a passion for what is actually inside.
The same holds for a ?S?. Its important specifications are the reference values, sample clock, and modulation order. Yet designers haven’t experimented with and eventually used them because, until recently, individual ?S?s weren’t commercially available.
For bipolar references, where logic high represents positive and logic low represents negative, an XNOR gate functions as a single-bit multiplier. For two analog inputs (A1, A2) and their corresponding uncorrelated densities (d1, d2), the XNOR of the two densities is equivalent to the product of the two analog inputs.
This is shown in the equation:
FROM THE BENCH
To build a mean-squared ADC, I built two ?S?s with two switched capacitor blocks in a Cypress CY8C27443. Both are single-order modulators with ±1.3-V references. One is clocked with 1 MHz while the other with 500 kHz. Both are fed the same analog input, and their outputs are XNORed with built-in programmable logic. With the same input and different clocks, the densities are guaranteed to be uncorrelated (Fig. 1).
The input is a 9.3-kHz, 2.2-V p-p sinusoid. The top digital stream is the density output of the 1-MHz-clocked ?S?. Note that the density is highest at the peak of the signal and lowest at its valley. The middle digital stream is the density output of the 500-kHz-clocked ?S?. Except for being half the frequency, it closely resembles its predecessor.
The bottom stream is the output of the XNORed logic streams. Its output is mostly high for the peak and valley of the input signal. To filter these streams, I used an oscilloscope in the average mode. It really isn’t a very good filter but it will show the potential of this technique (Fig. 2).
The top two streams resemble the input while the lower filtered stream is the product of the two filtered streams. As a result, the signal has been squared. An ordinary delta-sigma ADC produced the mean of the input. Using this technique, it’s possible to produce the mean of the input squared. Connect this output to a digital filter and you have a mean-squared ADC (Fig. 3). This filter will produce the mean of the input squared. Conversion to RMS only requires a square-root operation on this means-squared result.
To summarize, a typical delta-sigma ADC produces an answer that is the mean of the input. The use of an additional DSM now allows the mean of the input squared to be determined, with resolution dependent upon how long the stream is analyzed. As such, this filter allows you to move much of your signal processing from a microcontroller or DSP to less expensive logic gates.