Electronic Design

Use PWM To Maintain Motor Speed And Phase While Eliminating Loop Filter

In designing a simple spectroscopy setup, we needed to synchronize the speed of a small, inexpensive dc motor precisely to 6000 rpm (100 Hz). Our first idea was to take a phase-frequency detector type of phase-locked loop (PLL), the CMOS 4046, to maintain not only the speed, but also the phase to the reference signal. 1 In the classical approach, the motor’s speed is modeled as a firstorder time delay over time. Some math is done to obtain a good starting point to design the PLL’s important loop filter. This signal serves as an error signal that feeds the motor’s power amp.

Our solution, however, needs only a few parts and omits the loop filter entirely (see the figure). A drum on the motor shaft has a small black bar that acts as a light interrupter for a reflection optocoupler (OPB704a). Small positive-going pulses from Q2 drive two Schmitt-trigger inverters (40106). One inverter feeds an output pulse and the other closes the PLL’s feedback loop.

The LVCMOS reference input signal (Ref in) is attenuated and “supply-centered” with R1-R3 to obtain the best PLL performance. The PFD output directly drives op-amp IC3a. The op amp acts as a comparator and generates a pulse-width modulation (PWM) signal that drives the inverter, IC3b. The small TTL MOSFET, Q1, performs as a chopper to power the dc motor.

The circuit works well from 30 to 150 Hz. For speeds that are greater than 70 Hz, the speed deviation is within 0.02%. Load regulation is good because of the use of PWM. In the conventional solution, additional circuitry is frequently needed to compensate the armature resistance losses by measuring the motor current in order to make the motor stiffer. The PWM signal also eliminates the need for these adjustments. Because no pot is used in the circuit, it can be used with a lot of different low-power dc-motors without changes.

This circuit performs a lot of switching. Consequently, capacitors C1, C2, and C3 are used to decouple IC1, IC2, and IC3. C4 is employed to avoid ringing.

Reference:

1. R.E. Best, Phase-Locked Loops, 5th edition, McGraw-Hill, New York, 2003

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