Measuring key characteristics of high-speed pulses such as frequency, amplitude, and pulse width for simultaneous pulses that overlap in time has long been an issue in design. To solve that problem, engineers developed and refined the monobit receiver1.
The system includes RF signal shaping and filtering functions, a latched comparator (which is a single-bit analog-to-digital converter, or ADC), a demultiplexer to interface the high-speed digital data to commercially available FPGAs, and advanced digital-signal-processing (DSP) algorithms to extract the frequency and phase information.
The high-speed latched comparator (monobit ADC) is the key enabler of the monobit receiver design. Its function is to accurately digitize the input signal at the correct times. Two of the key specs for the monobit ADC are input analog bandwidth and thermal offset voltage.
Input analog bandwidth determines the maximum signal frequency that can be sampled. It is important in a bandpass sampling configuration, where the signal frequency can be greater than the sample frequency (see “Bandpass Sampling").
Thermal offset voltage is analogous to the input hysteresis for high-speed measurements. In the monobit receiver application, where the monobit ADC must make accurate decisions relative to a threshold voltage for input signals with varying histories in the time domain, it is important to minimize the dependency of the threshold voltage on past signal conditions.
Such variations of the threshold voltage can be seen as a thermal offset voltage, because the threshold voltage is shifted by thermal asymmetries that result from the electrical asymmetries in the differential datapath in the monobit ADC. This thermal offset voltage depends on the input data, and it is typically more significant than the dc hysteresis.
The output from the monobit ADC is a high-speed digital signal at many gigabits per second. To interface it to commercially available FPGAs that generally have low-voltage differential signaling (LVDS) I/O at up to 1 or 2 Gbits/s, a high-speed demultiplexer is needed to deserialize the high-speed bit stream into parallel lanes at lower speed. For example, a 1:8 demultiplexer can demultiplex a 10-Gbit/s highspeed bit stream to interface to an FPGA at 1.25 Gbits/s.
The single-bit digitization in a monobit receiver enables sampling at very high speeds. However, the tradeoff is that quantizing to only one bit generates a large number of spurious frequencies. Therefore, DSP is required to resolve the difference between the real signal frequencies and the spurious frequencies, via thresholding or other techniques. An additional requirement is to perform this signal processing in real time, within the power constraints of the system.
A MONOBIT RECEIVER PROTOTYPE
Figure 1 illustrates a design example of a monobit receiver developed by LNX Corp. for frequency measurement over the 0.5 to 18 GHz band. Target characteristics appear in Table 1.
The LNX Monobit DIFM (Digital Instantaneous Frequency Measurement) is based on a very high-speed monobit ADC. Multiple channels are required to cover the full 0.5- to 18-GHz band. However, the LNX design uses bandpass sampling techniques or direct digital down conversion to eliminate intermediate, mixerbased down conversions. All of the digital processing is performed in a single FPGA.
RF FRONT END
The RF front end contains:
• A limiting amplifier: The limiting amplifier has an operating bandwidth of 0.5 to 18 GHz. The loss of the frequency multiplexer, including the power divider and filters, will be approximately 12 dB. The power output of the limiting amplifier is less than +10 dBm.
• A frequency multiplexer: The partitioning of the 0.5 to 18 GHz frequency spectrum depends on the maximum sample rate allowed by the digitizer coupled with the ability to handle the demultiplexed data rate.
• Digitization and demultiplexing: The high-speed digitization is performed using Inphi’s 1385DX 12.5 Gbit/s 1:8 demultiplexer, which has a high-sensitivity latched comparator front. The 1:8 demultiplexer can be clocked at rates up to 12.5 Gbit/s.
The input amplitude to the demultiplexer is 500 mV p-p (–2 dBm). This sets the output power requirement of the limiting amplifier. The demultiplexer provides a demultiplexed 8-bit value and FS/16 data clock. For example, if the clock/sample rate for each channel is 8.192 GHz, then the data rate after demultiplexing is 1.024 Gbits/s. The clock is aligned so clock transitions occur in the middle of data transitions, simplifying clocking at the destination.
A number of different processing techniques can be used to perform the frequency measurement. Two particularly strong techniques are fast Fourier transform (FFT) processing and delta-phase processing.
A significant advantage of the monobit receiver is its ability to process simultaneous signals. An FFT can be used to exploit this feature. Figure 2 shows the results for two tones separated by 90 MHz sampled at 10 Gsamples/s. Each peak is clearly discernible. However, there are some disadvantages.
First, the FFT algorithm is computationally intensive, especially for long data frames. Data must be processed as blocks or frames of data. It may be advantageous to overlap the data frames in time, but this increases the amount of processing required. But because the raw data consists of a single bit, a zero or a one, many operations are trivial multiplications by a 0 or 1.
Second, the frequency resolution of the FFT is determined by the sampling rate and number of samples, or Fsample/ no_of_points. For example, a 100 ns record, sampled at 10 Gsamples/s, will have 1000 points and a frequency bin spacing of 10 MHz.
Delta-phase processing, another technique to measure frequency, is based on a delta-phase calculation. This technique isn’t as computationally intensive, but it doesn’t perform well with simultaneous signals. The frequency is measured by determining df/dt.
Phase values are generated from the amplitude values by a number of steps. For example, bandpass filtering and sampling translates an FS/2 block of spectrum to the first Nyquist zone from 0 to FS/2. The data is multiplied by a complex multiplier to shift the spectrum from – FS/4 to + FS/4.
The data is converted to a complex representation with in-phase and quadrature components. The conventional way to generate in-phase and quadrature components from a real signal is to do a Hilbert transform. The complex multiplication eliminates the need to do it as a separate step.
The phase is calculated by taking the arctangent of the in-phase and quadrature components using a lookup table. Finally, delta phase is calculated by taking the phase difference between successive samples. The delta-phase values can be averaged over a period of time (such as an input pulse width) to improve the accuracy.
Data was collected at a variety of sample rates, input frequencies, and signalto- noise ratios, and it was analyzed and processed using both FFT and delta-phase processing techniques.
Monobit receivers are a promising emerging solution for measuring simultaneous frequencies of high-speed pulses in real time. The critical elements of a monobit receiver system are the highspeed latched comparator (single-bit ADC), the demultiplexer to interface the highspeed digital data to commercially available FPGAs, and advanced DSP algorithms to extract the frequency and phase information.
1Tsui, James B. Y. " Two signal monobit electronic warfare receiver." US Patent 5793323. 11 Aug. 1998.
MICHAEL GRODEN, VP of digital Technology at lnX corp., holds a BSee from cornell University.
FRANCIS HO, senior director of business development at inphi corp, received his Phd in physics from Stanford University and his BS in physics from caltech.