Electronic Design

Vocal-Aural Feedback Digital Delay Device

When humans speak, many complicated, interrelated, and not completely understood neural and muscular processes must all coordinate. Most of these processes aren’t accessible to simple investigation, but one important speech-production mechanism is subject to easy and harmless experimentation. It’s based on the obvious fact that we normally hear our own voice whenever we talk and instinctively rely on this realtime feedback to aid in the production of fluent speech.

If a time delay of the right duration (0.2 to 0.5 seconds) is inserted in this vocal-aural feedback pathway, normal speech becomes amazingly and fascinatingly difficult. Some interesting insights (not to mention amusement) can be gained by experimenting with this effect. Moreover, there’s evidence that speech therapy involving sessions of talking under delayed aural feedback can help improve common and sometimes severe speech handicap: stuttering.

The circuit described here provides an adjustable, battery-powered, audio delay that’s well suited for such experimentation and therapy. Hybrid analog/digital delay techniques are employed to allow simultaneous record and playback.

An elementary 250-kHz samplerate delta-sigma 1-bit ADC (U1B, U2B, and Q1/Q2) converts audio from the electret microphone M1 into a serial binary stream at U2B. U2B’s output stream is integrated by R1C1, buffered by Q1/Q2, attenuated by R8 and R7, and fed back to U1B, thus closing the delta-sigma modulator loop.

Including the Q1/Q2 follower and R8/R7 attenuator inside the modulator feedback loop may look weird. However, it’s necessary to duplicate as closely as possible the U2A + Q3/Q4 DAC output stage (described below), and thereby compensate via preemphasis for the harmonic distortion inherent in such simple audio driver and filter circuits. In other words, by generating a bit stream that forces Q1/Q2 to accurately track the incoming audio, the delta-sigma modulator will automatically precompensate for Q3/Q4 nonlinearity. Using this technique, adequate overall reproduction fidelity is achieved.

For this trick to work, the Q1/Q2 and Q3/Q4 audio pairs must be at about the same temperature (to assure tracking of VBE voltages) and must be loaded equally. For this reason, R8 ¦ ¦ R7 has been selected to approximate the 68-Ω series-connected headphone impedance.

The 250-kHz bitstream from U2B is input to the adjustable length (512 bit to 256 kbit) serial memory comprising octal tristate register U4, static RAM U5, and adjustable-modulus address counter U2D, U2C, U3B, and U6. Depending on which one (or none) of the eight delay-set switches S1 through S8 is closed, the address counter will implement an effective modulus of 6 to 14 bits. The resulting serial memory continuously executes read-modify-write cycles in response to clock pulses from the 250-kHz squarewave clock formed by U1A and U3A.

On the 0/1 transition of U3A’s Q output, U4 assembles a byte, the MSB bit of which is the ADC output bit, and the other seven consist of the previous contents of the current SRAM address shifted one place. The result is then written to RAM on the 1/0 clock transition to be retrieved from 64 to 16384 pulses later. When that happens, the bit pattern will be shifted another bit position and rewritten until each bit eventually appears on U4 pin 16 for output to the U2A and Q3/Q4 DAC. Thus, from 512 to 256K clock cycles of delay may be imposed between ADC and DAC, producing audio delays of 2 ms (512/250 kHz) to 1 second (256K/256 kHz).

Other circuit features include automatic turn-on whenever the stereo headphones are plugged in, and the use of rechargeable batteries. Four AA NiCds will support more than 24 hours of operation between chargings. Recharge from a typical unregulated “9V” dc wall transformer (11 V actual) takes about 12 hours.

See associated figure

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