Electronic Design

What's All This Layout Stuff, Anyhow?

I’ve always been interested in the layout of things: bikes, cars, pc boards—and ICs. Sometimes it is just the compactness. Back in 1974, I got on a plane to San Francisco with my usual pad of quadrille paper, planning to draft (on the plane) an improved layout for a D flip-flop in CMOS. I got a couple of glasses of beer and soon concluded that I had no idea how to lay out a flip-flop. I went to sleep.

The next day, I discussed this with the Amelco guys, and they showed me their layout. I went back to my room and came up with a real good layout, noticeably more compact. Then the Amelco guys looked at it and made a couple small improvements. And then I added some tiny help.

Shortly we agreed there was no more room for improvement, and we were happy. One of the challenges was making this layout reasonably small, with minimum height, even if it was wide, so we could lay out a cascade of 16 flipflops in a stack.

Other times, the layout of linear ICs gets more interesting— for all sorts of reasons. Matching. Thermals. There are more than 50 rules for making transistors and resistors that match. Some have to do with “dummy” resistors or “dummy transistors.” Or dummy metal. Sometimes these rules work well. Sometimes they seem to break down. Sometimes the rules contradict each other. Now what?

Many of you guys will recall my Oct. 1, 1996 diatribe about “Common Centroid Stuff” (see www.electronicdesign. com, ED Online 6121). A number of engineers had designed and published a computer program that (they claimed) could automatically lay out transistors or resistors to be “common centroid.”

But the computer program actually produced layouts that were not common centroid, just interdigitated. Making a common-centroid layout is usually very easy, using the rules of symmetry. A computer is no help at all. In fact, it’s quite unnecessary. On rare occasions, a slide rule is helpful, because you can use its log scale for a measuring stick.

Sitting on a Panel
Recently, I was sort of invited to join a discussion panel of engineers on computer-aided design (CAD) and design automation for linear circuits. I thought about it. I’ve done this before. I’ve been on panel sessions at conferences. I recalled what happened.

There were some CAD guys who argued “Anything you can do, I can do better—and faster.” There was no way to rebut them. They set their own rules for what they thought was important. They did not want to talk about thermals. Or crosstalk. Or good grounds, even.

Nothing is less fun than a circuit that comes out of fab fast—and doesn’t work right. I bet a lot of you guys will agree on that. So, hurrying is an interesting idea, but maybe not a good idea. We have seen layouts that were done “as quickly as possible” but led to bad results. Hot transistors with varying quantities of dissipation, adjacent to critical transistors. Noisy busses laid out alongside (or on top of!) critical analog circuits. Or laid out alongside of busses that were going to critical analog circuits.

The art of knowing which circuits are critical isn’t always written down, codified, or quantified. Some of those things are just wrapped up in the heads of experts. Young engineers usually need to get older heads involved in the layout, and this has almost nothing to do with the schematic.

Getting the schematic to work, and to run in Spice, is hard enough. Getting it transformed into a good layout is another art. So I talked it over with a couple colleagues, and we all decided not to take part in that panel session. There’s no point in going on a panel just to be the straw man that the CAD guys are going to be knocking down!

So I’m going to forecast that software guys and CAD guys will never stop bragging about how great they are, even though they cannot prove they are as good as they claim. I have been able to make some layouts that were very good. But I’m not permitted to brag about it. I can, however, help my friends make good layouts. This is true for pc boards, as well as for IC layouts—not to mention 3D layouts.


Comments invited! [email protected] —or:
Mail Stop D2597A, National Semiconductor
P.O. Box 58090, Santa Clara, CA 95052-8090

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