In the early '90s, many pessimists predicted that CMOS would hit a wall as it approached 100-nm and lower gate lengths toward the end of the century. But CMOS processes steadily marched forward, firmly upholding Moore's Law.
Today, semiconductor IC suppliers are shrinking this technology even further by scaling design rules from 0.13 µm down to 90 nm (or 0.09 µm). DSP leader Texas Instruments provides a good example. Its recent 90-nm CMOS process can continuously scale for next-generation mixed-signal SoC chips to achieve as small as 37-nm gate lengths with an oxide thickness of 1.3 nm.
But Texas Instruments is not alone. Intel has un-wrapped a similar node for future processors. The company promises to keep doubling the transistor density on-chip in accordance with Moore's Law until the end of this decade. A new transistor structure developed by Intel researchers will help the microprocessor giant maintain this pace for some time.
Other major semiconductor players like STMicroelectronics and Philips Electronics, in cooperation with Taiwan Semiconductor Manufacturing Co. (TSMC), are pooling their re-sources to attain 90-nm capability. Their goal is to quickly migrate to 65-nm and finer geometries.
CMOS has obtained a new lease on life. For now, even the pessimists agree that it will perform until at least the middle of the next decade. Some experts say that CMOS will run out of gas at around 10-nm gate lengths between 2010 and 2015. Well, there's time to overcome hurdles and prove the pessimists wrong again.
The progress of CMOS bodes well for digital circuits. But can analog and mixed-signal circuits also continue to scale to stay in pace with digital circuits and tap the benefits of CMOS ad-vances? Judging from what's currently happening, they may benefit.
Only a few years ago, designers worried about the ability of high-performance analog and mixed-signal ICs to be made on lower than 0.5-µm CMOS processes. Only a few thought it was even possible.
Today, precision analog and high-resolution and high-speed data converters are manufactured in mainstream 0.35- and 0.25-µm CMOS processes. Designers have developed techniques and novel architectures that overcome the analog limitations of low-voltage CMOS processes. Loss of headroom, poor matching of MOSFETs, and capacitors and resistors are some challenges that have been addressed for voltages down to 3.0 V.
Now the goal is to migrate to the next level—0.18-µm and finer geometries—and to further narrow the technology gap between analog and digital circuits. That work is in full progress with the same zest and zeal. Several presentations at this year's International Solid-State Circuits Conference (ISSCC) have indicated success on this front, both at universities and at research labs of semiconductor companies.
Designers have combined novel architectures with MOSFET capacitors and clever compensation and calibration methods to realize delta-sigma modulators and oversampling data converters at sub-1-V supplies using 0.18- and 0.13-µm CMOS processes. Furthermore, self-adaptive silicon technology developed by startup Impinj promises to bridge this gap even faster than we can imagine.
Contrary to what the pessimists claim, improvements in the path to lower-voltage analog and mixed-signal CMOS designs go forth. Send me your thoughts on this issue.