Electronic Design
3D IC Technology Delivers The Total Package

3D IC Technology Delivers The Total Package

A never-ending parade of refinements to IC packaging gives engineers more choices than ever to meet their design requirements. With more radical approaches lurking on the horizon, that mix will become even richer.

Today, though, squeezing more functions into smaller spaces at a lower cost dominates, leading designers to stack more chips atop each other. Thus, we’re seeing the rapid ascent of 3D IC packaging.

The impetus behind 3D IC technology’s rise comes from the consumer market’s use of more sophisticated interconnecting methodologies to connect silicon chips and wafers. These wafers contain chips with continually shrinking line dimensions.

To scale down semiconductor ICs, finer line drawings are made on 300-mm wafers. Although most mass-produced ICs today are based on 55-nm design nodes or less, these design rules will shrink to 38 nm or smaller, and then down to 27 nm by 2013, according to forecasts by market forecaster VLSI Research Inc. (Fig. 1).

These downscaled IC designs accelerate the need for high-density, cost-effective manufacturing and packaging techniques, which will invariably challenge IC manufacturers to minimize the higher cost of capital equipment investments.

Many 3D applications still use traditional ball-grid-array (BGA), quad flat no-lead (QFN), lead-grid-array (LGA), and small-outline transistor (SOT) packages. However, more are migrating to two main approaches: fan-out wafer-level chip-scale packaging (WLCSP) and embedded-die packaging.

Presently, fan-out WLCSP is finding homes in high-pin-count (more than 120 pins) applications that use BGAs. Embedded-die technology favors the use of lower-pin-count applications that embed chips and discrete components into printed-circuit-board (PCB) laminates, and use microelectromechanical-system (MEMS) ICs (Fig. 2).

Researchers at Texas Instruments believe that WLCSP is heading toward a standardized package configuration. It could include a combination of WLCSP ICs, MEMS ICs, and passive components interconnected using through silicon vias (TSVs). The TSV’s bottom layer can be an active WLCSP device, an interposer only, or an integrated passive interposer. The top layer may be an IC, a MEMS device, or a discrete component (Fig. 3).

No matter the package type, though, as pin counts and signal frequencies increase, the need to pre-plan the package option becomes more critical. For example, a wire-bonded package with many connections may require more power-supply buffers on the chip due to high levels of inductance. The type of bump, pad, and solder ball placement also can significantly impact signal integrity.

TSVs: Hype Or Reality?

TSV technology is not a packaging technology solution, per se. It’s simply an important tool that allows semiconductor die and wafers to interconnect to each other at higher levels of density. In that respect, it’s an important step within the larger IC packaging world. But TSVs aren’t the only answer to 3D packaging advances. They represent just one part of an unfolding array of materials, processing, and packaging developments.

In fact, 3D chips that employ TSV interconnects aren’t yet ready for large volume productions. Despite making some progress, they’re limited to mainly CMOS image sensors, some MEMS devices, and, to some degree, power amplifiers. More than 90% of IC chips are packaged using tried-and-true wire-bonding means.

Speaking at this year’s ConFab Conference, Mario A. Bolanos, manager of strategic packaging research and external collaboration at Texas Instruments, outlined a number of challenges facing the use of TSVs in 3D chips. These include a lack of electronic design automation (EDA) tools, the need for cost-effective manufacturing equipment and processes, insufficient yield and reliability data involving thermal issues, electromigration and thermo-mechanical reliability, and compound yield losses and known-good die (KGD) data.

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Unlike conventional ICs, which are built on silicon wafers some 750 µm thick, 3D ICs require very thin wafers, typically about 100 µm thick or less. Given the fragility of such very thin wafers, the need arises for highly specialized temporary wafer bonding and de-bonding equipment to ensure the integrity of the wafer structure, particularly at high processing temperatures and stresses during the etching and metallization processes. After bonding, the wafer undergoes a TSV back-side process, followed by a de-bonding step. These typical steps result in higher yield levels for more cost-effective mass production.

Currently, there’s a lack of TSV standards on bonding and process temperatures and related reliability levels. The same is true regarding standardization of the TSV assignment of wafer locations. If enough IC manufacturers work on these issues, more progress can be made on expanding the roles of TSVs for interconnects. High process temperatures greater than 200°C to 300°C aren’t feasible for the economic implementation of TSVs.

Ziptronix Inc., which provides intellectual property (IP) for 3D integration technology, licensed its direct-bond-interconnect (DBI) technology to Raytheon Vision Systems. The company says that its low-temperature oxide bonding DBI technology is a cost-effective solution for 3D ICs (Fig. 4).

Nevertheless, many semiconductor IC experts view the industry at a crossroads of having to choose 2D (planar) and 3D designs. They see a threefold to fourfold increase in costs when going from 45-nm design nodes to 32- and 28-nm designs, considering the fabrication, design, process, and mask costs. Much needed improvements in lithography and chemical vapor polishing, as well as dealing with stress effects issues, make the 3D packaging challenge even more difficult. This is where TSV technology steps in.

France’s Alchimer S.A., a provider of nanometric deposition films used in semiconductor IC interconnects, has demonstrated that TSVs with aspect ratios (height to width) of 20:1 can save IC chipmakers more than $700 per 300-mm wafer compared with aspect ratios of 5:1 (see the table). This was accomplished by reducing the die area need for interconnection.

Alchimer modeled TSV costs and space consumption using an existing 3D stack for mobile applications, The stack included a low-power microprocessor, a NAND memory chip, and a DRAM chip made on a 65-nm process node. The chips are interconnected by about 1000 TSVs, and the processor die was calculated for aspect ratios of 5:1, 10:1 and 20:1.

IBM, along with Switzerland’s École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology (ETH), is developing micro-cooling techniques for 3D ICs, using TSVs, by means of microfluidic MEMS technology (Fig. 5). The collaborative effort, known as CMOSAIC, is considering a 3D stack architecture of multiple cores with interconnect densities ranging from 100 to 10,000 connections/mm2.

The IBM/Swiss team plans to design microchannels with single-phase liquid and two-phase cooling systems. Nano-surfaces will pipe coolants, including water and environmentally friendly refrigerants, within a few millimeters of the chip to absorb the heat and draw it away. Once the liquid leaves the circuit in the form of steam, a condenser returns it to a liquid state, where it’s pumped back to the chip for cooling.

Wire Bonding And Flip Chip

Wire-bonding and flip-chip interconnect technologies certainly aren’t sitting idle. Progress marches on for a number of flip-chip wafer-bumping technologies, including the use of eutectic flip-chip bumping, copper pillars, and lead-free soldering. Recent packaging developments include the use of package-on-package (PoP) methods, system-in-package (SiP), no-lead (QFN) packages, and variations thereof.

At the packaging level, 3D configurations have been well known for many years. Using BGA packages in stacked-die configurations with wire bonds is nearly a decades-old practice. For example, in 2003, STMicroelectronics demonstrated a stack of 10 dice using BGAs, a record at the time.

Certain 3D approaches like the PoP concept warrant special attention when it comes to high-density and high-functionality handheld products. Designers must carefully consider two issues: thermal cycling and drop-test reliability performance. Both are functions of the packaging materials’ quality and reliability. This becomes more critical as we move from interconnect pitches of 0.5 mm to 0.4 mm for the bottom of the PoP structure and 0.4 mm to 0.5 mm for the top.

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Samsung Electronics Ltd. has unveiled a 0.6-mm high, multi-die, eight-chip package for use in high-density memory applications. Designed initially for 32-Gbyte memory sizes, it features half the thickness of conventional eight-chip memory stacks and delivers a 40% thinner and lighter memory solution for high-density multimedia handsets and other mobile devices, according to the company.

Key to the package’s creation is the use of 30-nm NAND flash-memory chips, each measuring just 15 µm thick. Samsung devised an ultra-thinning technology to overcome the conventional technology limits of an IC chip’s resistance to external pressure for thicknesses under 30 µm. In addition, the new packaging technology can be adapted to other multichip packages (MCPs) configured as SiPs and PoPs.

“This packaging development provides the best solution for combining higher density with multifunctionality in current mobile product designs, giving designers much greater freedom in creating attractive designs that satisfy the diverse styles and thin-focused tastes to today’s consumers,” says Tae Gyeong Chung, vice president for Samsung’s package development team.

Market developments are also shaking up the QFN package arena. Germany’s Fraunhofer IZM has developed a chip-in-polymer process that imparts shock and vibration protection to the chip and lends itself to shorter interconnect distances to enhance the chip’s performance. The process starts by thinning the chip, then adhesively bonding it to a thin substrate.

This is all overlaid with resin-coated copper (about 80 µm for the resin layer and 5 µm for the copper surface). The resin is cured, and interconnect vias are laser-drilled down to the contact pads and plated with a metal. Then the redistribution layer on top is etched from the copper.

This process has been optimized in commercial production of standard packages like QFNs, without the need for specialized equipment or other delays. The use of polymer-embedded QFNs, essentially quad packs with no leads with the leads being replaced by pads on the chip’s bottom surface, is part of the HERMES project.

The goal of HERMES, which includes Fraunhofer and 10 other European industrial and academic organizations, is to advance the embedding of chips and components, both active and passive, to allow for more functional integration and higher density. The technology is based on the use of PCB manufacturing and assembly practice, as well as on standard available silicon dies, highlighting fine-pitch interconnection, high-power capability, and high-frequency compatibility.

The QFN package was selected because it’s more commonly found in small, thin appliances housing microcontroller ICs. Fraunhofer researchers believe that QFNs will take over many application niches held by other types of packages. The embedded QFN contains a 5- by 5-mm chip that’s thinned to about 50 µm. The package itself measures 100 by 100 mm. The 84 I/Os on the chip are at a 100-µm pitch (400 µm on the package).

Malaysia’s Unisem Berhad has unveiled a high-density leadframe technology, the leadframe grid array (LFGA), that offers BGA-comparable densities. The company says that it offers a cost-effective replacement for a two-layer FPGA package. Compared to a QFN package, it has shorter wire-bond lengths. In addition, it can house a 10- by 10-mm, 72-lead QFN package in a body size of 5.5 mm2.

“This package offers a better footprint with higher I/O density and better thermal and electrical performance. It is also thinner and, most importantly, offers a much better yield at front-end assembly,” says T.L. Li, the package’s developer.

Others working on embedding chips into various media include Dai Nippon Printing. It successfully embedded high-performance IC chips that are wire-bonded to a printed wiring board (PWB) inside a multi-layer PWB, citing unique buried bumped interconnections for its success. PWBs interconnect between arbitrary layers (via hole connections) with bumps made of high-electrical-conductivity paste, which are formed by screen printing.

Half-etching the base metal of the leadframe and making its inner leads longer will significantly close the distance between the chip and the leadframe it’s attached to, as well as drastically reduce the amount of gold wires for connections, resulting in lower manufacturing costs (Fig. 6). Mass production of ICs with more than 700 pins inside PWBs is scheduled for this year. Both active and passive components can be handled.

Work is underway to develop epoxy flux materials that improve the thermal-cycling and drop-test reliability shortcomings of conventional tin solder copper (SnAgCu). Developing such materials will help to advance the technology of 3D ICs using PoPs. Although PoP manufacturing employs commonly used tin-lead (SnPb) solder alloys, which offer advantages over SnAgCu materials, there’s a need for a lead-free compound to handle large high-density 3D PoP structures for consumer electronics products.

Henkel Corp. recently developed the Multicore LF620, a lead-free solder paste for a broad range of packaging applications. The no-clean halide-free and lead-free material is formulated with a new activator chemistry. Consequently, it exhibits extremely low voiding in CSPs via in-pad joints, good coalescence, and excellent solderability over a wide range of surface finishes.

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