Design Kit Cuts Verification Risks

A verification kit for wireless and consumer SoC designs that enables engineers to adopt advanced verification techniques with reduced risk and deployment effort has been developed by Cadence Design Systems. The Cadence SoC Functional Verification Kit provides an end-to-end methodology that extends from block-level verification to chip and system level advanced verification and includes automated methodologies for implementation and management. The kit also features example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish