California, U.S.A.: Synopsys has launched SuperSpeed USB 3.0 transaction-level models (TLM) supporting the Open SystemC Initiative (OSCI) TLM-2.0 API specification. The models are TLM representations of the Synopsys DesignWare SuperSpeed USB 3.0 Device and xHCI Host Controller IP.
The SuperSpeed USB 3.0 models enable pre-RTL and pre-silicon software development, verification, and architecture exploration. They are part of the DesignWare System-Level Library which features more than 100 TLM models, including models of the DesignWare Interface IP portfolio.
With the integration of SuperSpeed USB 3.0 into advanced SoCs and the increasing complexity of software stacks, the need to develop the associated embedded software as early as possible increases. The availability of ready-to-use SuperSpeed USB 3.0 TLM models, which are cross-verified with the corresponding DesignWare SuperSpeed USB 3.0 Interface IP and the associated Linux drivers, enables rapid development of virtual platforms for designs integrating the SuperSpeed USB 3.0 Interface.
Virtual platforms enable the concurrent development and debug of hardware and embedded software using an executable model of the hardware before RTL and first silicon are available. Like all models in the DesignWare System-Level Library, the SuperSpeed USB 3.0 TLM models work in any IEEE1666-compliant SystemC simulator, including Synopsys' Innovator for virtual platforms and VCS for functional verification. Adhering to the TLM-2.0 specification allows for easy integration with models coming from different sources, regardless of the simulation environment.