This simple design produces a sinewave that ranges from 2Hz to 20Khz using a CypressMicro PSoC chip. More information on these versatile devices can be found on their web page at:
According to Fourier Analysis, there is an infinite number of sine waves inside of the humble square wave. For example, a square wave of frequency f can be expressed in a Fourier series as:
Expanded, the above becomes:
If we set f to 1Khz and plot the first eleven terms of the above, we would get the waveform shown below in Figure 1:
The above is the addition of a 1Khz sinewave with increasingly smaller sinewaves that have frequencies of 3Khz, 5Kz, 7Khz, and so on. Even after 11 terms, we have a pretty jagged waveform.
To generate a sinewave from a squarewave, we are only interested in the first term of the Fourier series which is also called the fundamental frequency. If we could isolate that term of the equation, we could produce a pure sinewave with an amplitude of 4/π.
BPF2 to the Rescue
One method of isolating a single frequency component from a series of harmonics is to use a bandpass filter. Figure 2 shows a bandpass filter centered at 1Khz with a Q of 4. Superimposed on this graph are points representing the amplitudes of the first four terms of our Fourier series:
The red triangles are the amplitudes, in dB of the sine wave coefficients required to generate a squarewave. The green dots are the same amplitudes after the attenuation of the bandpass filter. We see from this that the first harmonic is about 20dB below the fundamental. The waveform resulting from this process will be what we want: a sinewave.
The bandpass filter in the PSoC tool kit has the nice property that allows the center frequency to be controlled by the sampling clock. The Q of the filter remains fixed regardless of the sampling frequency. By using a single clock to drive the filter sampling rate and to generate the squarewave input, we can build a digitally controlled sine wave generator. A block diagram of this approach appears in Figure 3.
The schematic of our circuit is shown in Figure 5. The only required component besides the PSoC chip is the digital encoder used control the counter period. The PSoC resource utilization can be seen in Figure 3. The design was implemented using a 16-bit counter, two 8 bit counters, a programmable gain amplifier, and a pair of bandpass filters.
Using the BPF2 design spreadsheet, a filter centered at 1Khz with a Q of 4 and an oversampling rate of about 50 was designed. The clock driving the filters has to be four times this sampling rate so the 16 bit counter is used to generate the 200Khz signal. To generate our 1Khz square wave, an 8-bit counter (Counter8_1), fed by the output of the 16-bit counter, was set up to divide by 200. The compare value was chosen to provide a squarewave output.
The output of the Counter8_1 was connected to P00. This, in turn, was externally connected to the input of the PGA amplifier at pin P03. To avoid saturation of the filters, the gain of the PGA was set to 0.75. The PGA output is then fed to the input of the first filter which is then followed by the second filter. The sinewave output is made available at pin P05.
Changing the value of the period register in the Counter16 module will produce a proportional change in the period of the output waveforms. The output frequency can be found by using the following equation:
The variable p is the value stored in the period register. By using an over-sampling ratio of 50:1, the useful frequency range of this design is 2 Hz to 20Khz or four decades. Going above 20Khz exceeds the maximum clock rate of the BPF2 stages. The lower limit is set by the maximum value of the period register. A log-log chart showing the relationship between output frequency and period is shown in Figure 7.
To provide a simple means of changing the output frequency, a Digital Encoder is connected to Port 1. The encoder is a pair of switches that open and close in quadrature as the knob is rotated. Referring to Figure 4, we see that clockwise rotation produces a pair of waveforms with channel A leading channel B. Channel A lags channel B with counterclockwise rotation.
The built-in pull ups of the PSoC chip were used to minimize parts count and pin P10 was set to interrupt on the falling edge.
Upon interrupt, Counter8_3 is used to provide about a 500usec delay to suppress switch bounce. P10 and P12 are then sampled. If P10 is not low then we assume that the interrupt was caused by switch bounce. If P10 is low then we sample P12. If P12 is high then rotation is CCW and we increment the period value. If P12 is low, rotation is CW which leads to a decrease in the period value.
If you want to minimize board space, this design could be completely contained in the 8-pin variant of the PSoC chip (CY8C25122).
There’s no reason that an encoder has to be used as the input mechanism. Another device or microprocessor could be used to provide the quadrature wave forms. Or, an RS232 block could be implemented in the PSoC chip that, with some additional software, could provide very fast updates to the period register.
Finally, the precision of the system could be better regulated with the addition of an external crystal to provide the system clock.