Electronic Design

# ED Helpline: Soft Start Circuit

Question:

"I am driving MOSFETs in a half-bridge configuration at 540 Hz with signals from an external unit (PWM controller is not being used to generate the switching pulse). Is there a soft-start circuit that ramps up the duty cycle from 0 to 50 percent that I could use to control the FETs and regulate the current over a period of approximately 150 ms?"

You can use 8-pin MCU from AVR or Microchip using Software PWM. It will be the most cost effective, if you have the resources. I can give the program for AVR if you need.

+++++++++++++

Generate a 540-Hz linear ramp signal using an LM555 triggered by the 540-Hz waveform. The ramp signal can then be "compared" to a copy of the external control signal (I assume this is just an "enable" signal) that has been put through a low-pass filter (RC network) such that it "charges" up from 0 (volts) to "half of ramp" (volts) in approx. 150 mS (giving 0-50% duty cycle output in this period). The low pass input will continue to charge past 50% duty cycle, so the comparator output will need to be "blanked" (AND gate) with the basic 540 Hz to limit the continuous output to 50% duty cycle.

This function can be accomplished using the LM555, an LM393, a couple of 1N4148 diodes and several passives (Rs and Cs) for the LM555 and the RC network. All inexpensive components.

+++++++++++++

What is the output wave shape of the external unit? If it is square, you may be able to use an AND gate to do the soft start; with one input connected to the output of the external unit, the other input connects a capacitor to ground. The top end of the capacitor connects to a resistor. The other end of the resistor connects to the output of the external unit.

The resistor and the capacitor will set the time constant of your soft start circuit.

+++++++++++++

I had occasion for this kind of circuit. At the time, I was using a Xilinx for all the system control, so I just added a couple of features -- a fixed period counter. An upper-limit counter for the pulse width, which started at 0 and counted up slowly at power-up or turn-on of the stage(to a maximum of 0.5x the fixed period counter). I then had an external A/D or comparator for current sensing to control the requested Pulse-width (PWM Count). The actual pulse was turned on at 0 in the period counter (if needed) and turned off by either the PWM Count or the PW Upper-Limit counter, whichever occurred first. The same algorithm is easily accomplished in software, if you have a microprocessor with PWM timer output.

I have been designing hardware for a long time, and always try to leave myself a lot of flexibility, so my preferred architecture is a "dumb" microprocessor combined with a "smart" programmable array. That way, I can multitask in hardware, offloading the micro, getting accurate and repeatable timing, as well as much more reliable software (less code and usually No OS is required).

Do you have any solutions to this design problem? Please e-mail your ideas to Lisa Maliniak, eMedia Editor.

Readers seeking help with their own design problems are encouraged to e-mail Lisa Maliniak, eMedia Editor, for posting in future editions of Electronic Design's Helpline.

TAGS: Microchip