Electronic Design

Illiac II Computer Shaping Up For Tests

Iliac II, the University of Illinois' scientific computer, is expected to be ready for its first system tests next spring. At that time, the arithmetic units, some of the control units, core storage, and some of the tape units should be completed.

At present, the repetitive parts of the arithmetic units have been run error-free, the first 4000 words of core storage are being debugged, and the computer's special buffer memory—or flow gate—is nearing completion. Illinois project engineers expect the computer to be doing useful work by the end of 1962.

The Illiac II is said to be the most asynchronous computer so far devised. Latest performance specifications given for the machine are:

  • Multiply time—6 to 8 µsec.
  • Add time—1.5 to 2 µsec.
  • Divide time—15 to 20 µsec.
  • Core cycle time—1.8 to 2 µsec.
  • Access time to fast buffer store—0.25 µsec.

These figures are for floating-point operations on 52-bit words, of which 7 bits form an exponent representing a power of 4 and 45 bits the fractional part.

Because the university will be the only user of Illiac II, the computer is being built with only 8192 words of core storage, divided into two units. These will be backed up by 65,536 words of storage on magnetic drums having an access time of 7 µsec once in synchronism. Illiac's designers say that computing time will be slowed only 10% or 15% by the lack of all-core storage, and that the savings in cost of hardware more than compensates for this.

One of the basic considerations affecting design of the computer was the inequality in speeds of arithmetic and storage operations. Because of the relative slowness of storage, Illiac II was organized so its programs require as few references to core memory as possible. Also, the core memories are designed to be fast in themselves and to be used in multiplex. To enhance the effects of these steps, fast controls were designed and the arithmetic unit and input-output devices were linked to the core memories. The design objective was to make the operating time for all devices roughly equal, and to run them concurrently.

To minimize access to core storage, Illiac is provided with a compact order code, fast storage of short loops, storage of intermediate results through the use of a fast buffer, and an organization that permits concurrent operation of core and arithmetic units, initial decoding of addresses, decoding of instructions, and transfers of memory blocks.

Also, to reduce the necessity for access to instructions, word length was increased and instructions were designed to be more powerful than usual for a given number of bits. The number of bits per instruction was reduced.

Another design feature allows a number of instructions held in fast transistor registers to be obeyed repeatedly without further reference to the core memory for instruction.

To reduce the number of bits per instruction, variable-length instructions are used in the Illinois computer. Long 26-bit instructions are used only where needed. The rest of the time, 13-bit instructions are used.

Because the computer is designed to be asynchronous to an unusual degree (which designers call speed-independence), control is critical and achieved in a novel fashion. In addition to interplay control and an arithmetic control that corresponds to the usual delayed control (DC), Illiac includes an advanced control. This circuitry processes every instruction; it's said to correspond to the memory bus, instruction unit, and look-ahead of the Stretch scientific computer, made by International Business Machines Corp. (Electronic Design, Nov. 22, 1961, p. 26)

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