Electronic Design

Improve Phase Margins In Buck Converter Loop Compensation

 

 

1 of Enlarge image
 

 

 

The phase margin in the compensation feedback loop of buck power converters is an indicator of both loop stability and the acceptability of the converter’s pulse response. The compensation loop typically incorporates resistor-capacitor networks attached to the controller IC’s internal error amplifier and must be designed in light of the second-order (resonant) LC filter on the converter’s output.

The conventional approach to selecting parameters for the loop, however, does not always provide the best phase margin. Shifting the compensation network’s zeros to lower frequencies than the filter poles can improve the phase margin by as much as 20°.

Conventional phase correction in buck converter design usually places the compensation network zeros directly into the second-order filter’s poles to cancel them out (see “Designing With The TL5001 PWM Controller” ).

Such compensation is incomplete, though, because the second-order LC filter’s and the two aperiodic compensating RC chains’ phase characteristics are shaped differently. The open feedback loop’s phase characteristics thus contain two humps, which lead to sub-optimal phase compensation.

While this analysis is for a buck power supply based on the TI TPS54310 controller, it holds true for any other buck converter design. In the output filter schematic (Fig. 1), RL is the load resistance, L is the filter inductance, C is the filter capacitance, and RC is capacitor C’s equivalent series resistance (ESR). MOSFET designates the power transistor. The filter parameters are:

(Eq 1)

It is easy to obtain the characteristic equation for the filter frequency response in a form that is convenient for a logarithmic interpretation:

 

(Eq 2a)

(Eq 2b)

(Eq 2c)

In addition to the output filter frequency response, we need the gain of the converter’s pulse-width modulation (PWM) stage. Note that:

VRAMP = 1 V – 0.75 V

is the IC’s internal oscillator ramp amplitude per the TPS54310 specification. Therefore:

PWM gain (GPWM) = VOUT/VRAMP = 4.8.

In log format:

LGPWM = 20log(GPWM) = 13.625

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The total frequency response for the power stage is then the product of the two:

LGNC(ω) = LGLC(ω) + LGPWM

and phase response is:

(Eq 3)

Plotting the power stage’s frequency response shows a phase correction at the high end of the frequency range, which is due to the ESR of capacitor C (Fig. 2).

The compensation amplifier utilizes the IC’s internal error amplifier (Fig. 3). It is intended to place zeros and poles so they compensate for the adverse phase shift in the output filter and suppress unwanted noise in the loop.

To obtain a good transient response, choose a unity gain frequency at around 30 kHz. The IC’s error amplifier unity gain bandwidth of 3 to 5 MHz allows you to neglect the error amplifier’s frequency response roll-off within the range up to 30 kHz. The compensation amplifier has a complex frequency response:

(Eq 4)

(Eq 5)

with:

R2 = 10 kΩ

The filter and compensation loop phase response derivatives are different, so it becomes clear that a complete phase compensation is impossible. It looks reasonable, then, to seek a means to reduce the total phase shift and thus increase the phase margin. Analyzing the phase margin plot shows that to beef up the phase margin, it is necessary to reduce the compensation frequency and move the right hump to the left by ωshift.

To determine the appropriate reduction the calculations below, express this shift in fractions of ωLC, which allows the drawing of a plot showing how the phase margin depends on the compensation frequency shift.

The pole at 1/\\[R2 × (C2 + C3)\\] sets the open loop unity gain frequency (fug), which is 30 kHz in this case. The zeros at 1/\\[(R2 + R3) × C1\\] and 1/(R4 × C2) should compensate for the poles of the output filter at ωLC – ωshift, where:

(Eq. 6)

The pole at 1/(R3 × C1) is positioned at almost the same frequency as the zero in the output filter to maintain the –20-dB/decade roll-off in the gain response. The pole at:

(Eq 7)

should be placed between half the PWM’s operating frequency and the operating frequency to minimize noise at the PWM comparator input. For this analysis, we will set the pole at 3/4 the operating frequency.

The sum of the modulator, the LC filter, and the error amplifier gains should be 0 dB at the unity gain frequency of 30 kHz. The modulator + LC filter gain at 30 kHz is:

LGmod_and_filter = LGNC(2π × 30 kHz) = –2.195

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The zeros have a gain at 30 kHz:

(Eq. 8)

Therefore the compensation network integrator should have a gain of:

(Eq. 9)

Note that:

20log(Gint) = LGint

So:

(Eq 10)

and:

(Eq 11)

But:

(Eq. 12)

So let:

CBeqv1 = C2 + C3

Then:

(Eq 13)

and:

(Eq 14)

Assuming that C2 >> C3, you can set C2 = CBeqv1. Choose R4 to position a zero at ωLC – ωshift, so:

(Eq 15)

and:

(Eq 16)

R3 and C1 are chosen to provide an additional zero at ωLC – ωshift and a pole at ωC so:

(Eq 17)

R3 × C1 = 1/ωC

Solving these two equations, obtain:

(Eq 18)

and:

(Eq 19)

So:

(Eq 20)

(Eq 21)

C3 is chosen to provide a pole at 250 kHz, so:

(Eq 22)

and:

(Eq 23)

Rewrite the formula for the frequency response of the compensation amplifier now, substituting known C2 and compensation frequency values for unknown components. The compensation network zeroes are positioned at ωLC – ωshift so:

(Eq 24)

(Eq 25)

Then:

Gloop(ω) = GCA(ω) × GLC(ω) × GPWM

(Eq 26)

with the 180° added to obtain the phase margin.

The plotted results for the different frequency shift candidates show that shifting the compensation frequency to lower values makes it possible to dramatically improve the feedback loop phase margin (Fig. 4).

Designers should choose an “early” compensation because the LC filter and RC networks have different slopes in their phase characteristics. The LC filter phase characteristic slope in the vicinity of resonance is much steeper than that of the second-order RC network.

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