Soitec and SEZ Collaborate to Accelerate Adoption of Strained SoI Substrates

The Soitec Group and the SEZ Group have initiated a joint development program (JDP) intended to speed the industrialisation of next-generation strained silicon-on-insulator (sSOI) substrates. Under the terms of the JDP, the two companies will leverage Soitec's experience in engineered substrates and SEZ's experience in single-wafer, wet-processing technology to develop new wet-etch processes designed to optimise total germanium removal in sSOI manufacturing.

Company officials said that effective and complete removal of germanium is a key step in the sSOI manufacturing process as silicon germanium (SiGe) must be used to produce the silicon-layer strain that is essential to sSOI's functionality. Ultimately, it is the combined power of this strained silicon layer and the SOI substrates that allow chipmakers to harness the performance and power dissipation benefits afforded by sSOI substrates. Single-wafer processing has emerged as a promising solution for enabling selective control during the germanium etching process—removing only the desired material without damaging underlying material layers.

Carlos Mazure, Soitec's chief technology officer, said: "This joint work is another step in Soitec's strategy to build the industry infrastructure that will ensure manufacturability and broad commercial availability of future generations of sSOI substrates. SEZ's single-wafer technology offers benefits for selective etch of SiGe that allows more efficient germanium removal. At the same time, Soitec and SEZ will work together to optimise quality, throughput and cost of ownership, creating a reproducible process that can potentially be used to manufacture other complex materials."

"We are pleased to be entering into this collaborative effort with Soitec," added Dr. Gerald Wagner, director of process development for SEZ. "SEZ is continually involved in research and development surrounding new materials and process solutions. Working with an industry leader like Soitec will enable us to access their extensive expertise in sSOI and other advanced substrates. By pairing the benefits of their Smart Cut technology with those of our single-wafer, wet-etch technology, we plan to develop a new process application that may prove essential to producing sSOI substrates in volume quantities."

Since introducing germanium-free sSOI substrates to the market last year, Soitec has investigated a range of manufacturing approaches. According to Soitec officials, using a controlled, single-wafer, wet-etch method presents the company with an opportunity to further perfect total germanium removal so that it can be done even more efficiently and selectively, while minimising the possibility of damage to the sSOI substrates.

For SEZ, this JDP broadens the applications for single-wafer technology, offering further evidence of the accelerating industry transition from batch to single-wafer wet processes. Integrated device manufacturers (IDMs) and foundries producing ICs with high-aspect-ratio, 90nm and smaller geometries are rapidly shifting to single-wafer manufacturing to take advantage of its cost and performance benefits. SEZ's spin-processing technology, the de facto standard for most back-end-of-line (BEOL) cleaning, etching, stripping and surface-conditioning processes, is now penetrating wafer manufacturing and front-end-of-line (FEOL) processes.

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