As the cost of fabricating an ASIC mask set climbs past half-a-million dollars and approaches 1 million dollars, the industry faces a significant challenge. The high cost of masks has started to limit the number of companies that can bring their creative solutions to fruition. It isn't just the high mask cost that's starting to stifle ASIC development, though. The prices of design tools have also been escalating as they're called on to perform tasks that are more complex because the chips that they help design are reaching new heights in density and speed.
The challenge to keep development spending in line will be a key aspect of any new chip company's business plan because the money supply of many startups has become scarce in this slow economic period. EDA tool suppliers have started to look at novel approaches to help defray the high cost of some critical point tools. These tools help with modeling, simulation, design-rule checking, placement and routing, and design verification.
Yet, many of these tools are used for only a limited time period during the entire design project. Therefore, companies are exploring week-to-week or month-to-month leasing options as a less expensive alternative to a full purchase or yearly lease of the tool.
When it comes to implementing the chip, the wide array of process technologies presents an almost bewildering array of options—feature sizes, copper versus aluminum for metal interconnect, bulk silicon versus silicon on insulator, and so forth. Several aspects are determined by the complexity of the chip being designed. Other aspects are determined by tradeoffs, like cost, made to ensure that the chip can be fabricated as economically as possible with as high a yield as possible.
The cost of the 20 or more masks necessary to fabricate the chip is an overwhelming consideration, though. Several fabrication companies have created a shared-wafer manufacturing approach that helps reduce the cost by sharing a portion of the overheads across several company designs. But this method limits any customization that designers may need to best optimize the physical or circuit implementation.
Advances in high-density FPGAs have also helped provide an alternative to some ASIC prototyping and even some low-volume production. The megagate-complexity FPGAs allow designers to prototype complex ASICs without the high mask costs. However, if used in production runs, the FPGA costs would be considerably higher than those of a custom chip. Additionally, in many cases, the logic performance doesn't come close to the final performance goal of the ASIC implementation, which might run 50% to 200% faster than the FPGA implementation.
Several companies that supply ASICs have started developing a new technique that combines some aspects of gate arrays, several standard cell approaches, and a lot of ingenuity to bring down the nonrecurring engineering and mask costs typically associated with ASICs. At the same time, the approach enables integration and performance levels that come close to what a custom chip might deliver.
Sometimes known as "platform chips," the concept starts with a prefabricated array of logic elements (gates, or more complex logic building blocks) and perhaps embedded memory and some high-speed I/O buffers. The array might use six or seven levels of metal, but the first two or three are predeposited to form the basic elements.
These half-completed wafers can then be stored until needed. Only a relatively small number of masks must be created to configure the final logic, bringing the mask cost down to a few hundred thousand dollars, and shortening the turnaround time compared to a full-custom design. Back in the late 1980s, a number of companies tried a slightly similar approach, but the integration levels didn't permit the system-level solutions that are now possible. Maybe it's time to revisit this approach, only with today's processes and design tools to cut some costs and deliver system-level solutions.