Dr. Sanguinetti has been active in computer architecture, performance analysis, design verification, and electronic design automation for 30 years. After working as a design verification engineer at Ardent Computer and NeXT Computer, he founded Chronologic Simulation in 1991 and was the principal architect of VCS, the Verilog Compiled Simulator. He was a co-founder of C2 Design Automation, now Forte Design Systems, where he continues to serve as Chief Technical Officer. He was recently honored as a fellow of the ACM. He has 15 publications, one patent, and authored the Verilog Online Training course. Dr. Sanguinetti’s Ph.D. is in Computer and Communication Sciences from the University of Michigan.
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