Actel Corporation has begun shipping the Actel Fusion programmable system chip (PSC), a series of single-chip field-programmable gate arrays (FPGA) that integrate mixed-signal analog, flash memory and FPGA fabric, allowing designers to move quickly from concept to completed design.
Actel president and chief executive officer John East said the Fusion PSCs bring the benefits of programmable logic to application areas that, until now, have been served by discrete analog components or mixed-signal ASIC solutions. "Designers will be able to treat the Fusion PSCs like a mixed-signal ASIC without all the ASIC penalties of long design cycles and high costs," he said, adding that the new devices can be used together with Actel's ARM7 and 8051-based soft MCU cores.
The Actel Fusion devices integrate a configurable 12-bit successive approximation register (SAR) A/D converter with frequencies up to 600 ks/second. The analog block supports MOSFET gate driver output and multiple analog inputs from –12 V to +12 V with an optional prescaler, enabling direct connection and control of a wide variety of analog systems such as a voltage, differential current or temperature monitor.
The devices allow designers to reconfigure analog block settings to perform different functions by downloading data from embedded flash memory. Each device includes up to 1Mbyte of embedded flash memory that offers 60-nanosecond random access and 100 MHz access in read-ahead mode. The flash memory offers a user-configurable data bus supporting x8, x16 and x32 bit widths. It also offers error correction circuitry (ECC) with single-bit error fix and two-bit error-detect capabilities. Pseudo EEPROM can be achieved with endurance extender IP available from Actel.
Fusion peripherals include hard analog IP and hard and/or soft digital IP. Peripherals communicate across the FPGA fabric via a layer of soft gates--the Smart Backbone, which integrates a micro-sequencer within the FPGA fabric and will configure individual peripherals and support low-level processing of peripheral data.