Auto Electronics

ARM processor features ECC support, optional FPU

ARM (www.arm.com) has introduced the Cortex-R4F processor for automotive applications such as next-generation anti-lock braking and vehicle stability. Product manager Richard York said the new chip offers options including integrated error-correction codes (ECC) logic and a floating-point unit (FPU) optimized for single-precision arithmetic.

York noted that system-wide error detection is increasingly important because of the large volumes of data transmitted throughout next-generation SoCs in automotive applications. Integrating ECC logic within the processor pipeline eliminates the need for external ECC logic, avoids performance degradation, and scans data continuously for errors. The logic corrects single memory errors, rather than just stopping the system and communicating the error, and detects double-bit errors.

He added that the memory protection features in the new CPU are critical to applications based on the OSEK standard for open-ended architecture (www.osek-vdx.org), the JasPar Automotive software platform architecture (www.jaspar.jp) and the AutoSAR runtime environment (www.autosar.org). Robert Bosch GmbH (www.bosch.com) is using the new processor in an application that was not disclosed.

York said the R4F FPU is optimized for the single precision processing, which is commonly used in automotive applications and twice as fast as double precision.

The Cortex-R4F processor features a dual instruction issue capability to deliver more than 800 Dhrystone MIPS in a performance-optimized 90nm implementation, based upon an ARM Artisan Advantage library. The processor occupies less than 1mm x 1mm and consumes less than 0.27mW/MHz in an area-optimized 90nm implementation. Relaxed timing on the level 1 memory allows the use of dense, low power RAMs.

Like its predecessor, the Cortex-R4, the R4F offers ARM instruction set compatibility; configurability during synthesis, to optimize the processor for different applications; caches; tightly-coupled memory; DMA, and debug facilities.

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