Designers are employing a range of techniques, like Ambiq Micro’s subthreshold designs to reduce power consumption while delivering high performance devices. NXP is employing 28-nm FD-SOI (28FDS) technology with its new i.MX 7ULP family, targeting applications ranging from wearables to automotive. The i.MX 7ULP family is the low power migration path (Fig. 1) from the popular i.MX6 family.
1. NXP’s 28-nm FD-SOI technology is used to build the i.MX 7ULP family that replaces the low end of the popular i.MX6 family.
FD-SOI utilizes an ultra-thin buried oxide layer (Fig. 2) to improve electrostatics, thereby enabling shorter gate lengths. It also makes the gates immune to latch up. The approach provides a 10× to 100× improvement in soft error rate (SER) performance.
FD-SOI also helps in reducing device parasitics, and the use of device back bias allows performance to be maintained while lowering VDD. There is improved analog peripheral performance with higher gain, better matching, and lower 1/f noise enhancements. The gate-first integration removes density rules for precision analog. Device tuning with back biasing is employed to compensate for process variation.
2. FD-SOI utilizes an ultra-thin buried oxide layer.
NXP developers used domain and subsystem optimizations to design the chips, along with a custom standard cell library with mixed voltages. They employed a large dynamic gate and body biasing voltage (VBB) range to address speed and power requirement tradeoffs and to deliver an extreme low leakage implementation.
The system actually use a dual-core, asymmetric design with an ARM Cortex-A7 paired with an ARM Cortex-M4 (Fig. 3). The cores can operate independently when it comes to operation and sleep mode. Versions of the i.MX 7ULP are available with the 3D Vivante GC7000 NanoUltra 3D GPU with a low-power single shader, or the GC320 Composition Processing Core (CPC) for 2D graphics support.
3. The i.MX 7ULP uses a dual core, asymmetric design with an ARM Cortex-A7 paired with an ARM Cortex-M4.
The chip has secure boot support for both cores and the QPSI interface supports on-the-fly encryption and eXecute-in-place (XIP) support. The Cortex-M4 has access to the typical serial and digital peripherals as well as a set of dual-channel 12-bit ADCs and DACs. The Cortex-A7 sports USB 2.0 host and OTG interfaces. The TrustZone hardware support includes a true random number generator (RNG), as well as crypto hardware with AES-128/256 support and secure fuses for unique identification, plus secure storage. The system has tamper detection support and a secure real-time clock (RTC).
The chips are available in 14-mm by 14-mm or 10-mm by 10-mm BGAs with a 0.5mm pitch. They are supported by NXP’s CodeWarrior development tools, along with a Linux or Android ecosystem for the Cortex-A7 and FreeRTOS for the Cortex-M4’s real-time capability.