Fujitsu Microelectronics America has integrated its multilayer, 2-D/3-D MB86296 (Coral) graphics display controller (GDC) with a 32-bit ARM926EJ-S CPU core to craft the MB86R01 (Jade) a system-on-chip for automotive graphical display applications.
Built using Fujitsu’s 90 nm CMOS process technology, the R01 targets high-end, high-volume embedded automotive graphics applications such as navigation systems, graphical dashboard systems, heads-up display (HUD) units and rear-seat entertainment.
Dan Landeck, senior marketing manager for graphics display controllers at FMA’s Embedded Systems Business Group, said that integrating the graphics display controller and 32-bit microcontroller on a single chip can lower bill of materials costs by 30% or more, in addition to conserving space and reducing power requirements. “Compare a single unit at 2 W against a graphics display controller at 2 W plus a processor that consumes several watts,” he said.
Fujitsu’s MB86296 provides a rendering engine for 2-D/3-D graphic acceleration functions, a geometry processor supporting floating-point transformations for smooth graphics animation, and a dual-display capability (2 x RGB digital output), which allows different content to be shown on two connected screens. Landeck said the 296 chip in the R01 is actually a hybrid that incorporates features from Fujitsu’s MB86297 (Carmine) GDC chip--GDC--support for two video inputs and two different screen resolutions.
The R01 includes built-in alpha blending, anti-aliasing, and chroma-keying, and it supports display resolutions from 320 x 240 up to 1024 x 768. Dual-digital video-input formats include YUV, RGB and ITU656. Other features include bit-blt (blitting/bit block transfer), in which multiple bitmap patterns are combined; texture mapping (units up to 4096 x 4096); alphabit-blt and ROP2 (binary roster operation) functions, and six layers of overlay display.
The ARM926EJ-S is a fully synthesizable processor with a Jazelle (Java Acceleration) technology-enhanced 32-bit RISC CPU, 16 kB instruction cache, 16 kB data cache, 16 kB instruction tightly coupled memory, 16 kB data tightly coupled memory, and memory management unit (MMU). The CPU runs major operating systems and middleware, including Microsoft Windows CE, QNX, Wind River VxWorks, Linux and Itron.
The R01 incorporates ETM9 (embedded trace macrocell) debug/trace facility and JTAG ICE interfaces as well as I2C and I2S interfaces, PWM, SPI, UART, GPIO, and an external interrupt, plus 8-channel DMA and 32-bit timers. Its core frequency is 320 MHz generated by the on-chip PLL.
Onboard peripherals include an A/D and a D/A converter, unified DDR2 memory (up to 128 MB) supporting 320 Mbps, a parallel flash/SRAM host interface with decryption engine, parallel ATA, SD-card, CAN interface, Media LB, and USB 2.0 (host and function).
Packaged in a 484-pin BGA, the R01 requires a supply voltage of 3.3 V (I/O), 1.8 V (DDR2), 1.2 V (internal), and is designed to operate over a temperature range of -40 °C to +85 °C.