Electronic Design

Initiative Promises High-Capacity SoC Design Environment

NEC Electronics Inc., Santa Clara, Calif., recently launched an initiative to provide a system-on-a-chip (SoC) design environment capable of enabling a three-month turnaround time—from system specification to tape-out—for designs consisting of 30 million gates or more. Known as the ACE-2 Initiative, this three-year, $30 million development effort will cut a typical ASIC SoC design schedule by two-thirds.

Phase one of the Initiative is expected to be completed by March. During this phase, tools will be developed to support software design and verification, hardware verification, intellectual property (IP) modeling, and register-transfer-level (RTL) planning and sign-off. These tools will be able to work at a higher level of design abstraction. They also will address both system and silicon implementation for markets such as communications, consumer, PC/PC peripheral, and automotive.

The resulting design environment based on these tools will enable concurrent design and early troubleshooting capabilities for use during design planning and system and performance evaluations. Additional phases will see NEC working toward integrating performance analysis, hardware design, market-based hardware and software tradeoffs, and system analysis.

To accomplish this task, a group of 50 NEC engineers will team with select electronic design automation (EDA) and design service companies to define and design the new environment. Being supervised by NEC Electronics in the U.S., this group also will be responsible for driving system-level EDA-related standards in tool interfaces, libraries, IP, and methodologies.

For more information on the initiative, check out NEC Electronics' web site at www.nec.com.

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