Mentor Graphics said that STMicroelectronics has adopted Mentor’s TestKompress automatic test pattern generation (ATPG) product into its standard 65nm and 45nm design kits. The test flow will enable high-quality scan-based production testing for automotive and other applications.
“We’re benefiting from a very fruitful collaboration to incorporate Mentor Graphics’ Design-For-Test (DFT) technology into our advanced nanometer design flows starting at 65 nm and below,” “With new failure mechanisms at advanced nodes, limitations on IC pins available for testing, and the need to employ better self-test in the field, the range of emerging testing requirements has significantly increased,” said Roberto Mattiuzzo, Digital Test Solutions manager of STMicroelectronics’ Technology R&D, Central CAD & Design Solutions. “We are therefore pleased to add Mentor Graphics in the portfolio of EDA solutions supported by STMicroelectronics in the Design-For-Test (DFT) area.”
The firms said the move to smaller geometries introduces new subtle failure mechanisms that can be missed by relying solely on traditional scan testing using only static fault models. Applications that demand the highest quality devices require additional test patterns that specifically target these new failure mechanisms. STMicroelectronics employs a variety of manufacturing tests including timing-aware at-speed tests and layout-aware bridging tests to ensure the quality of their semiconductor products. Mentor’s TestKompress compression technology allows these additional tests to be added while at the same time reducing test data volume and test time. STMicroelectronics is also using Mentor DFT tools to add in-system testing to its high-reliability products to enable a fast check of system integrity and simplified trouble-shooting in the field.