Electronic Design

UML: A Next-Generation Language For SoC Design

The Unified Modeling Language (UML) has already received considerable acceptance in the domain of telecommunication and automotive systems, and now we see emerging activities in the field of SoC design \[1-3\].

Although different UML diagrams are being used for various purposes, such as testbench description and the specification of requirements, architectures, and behavior, there has yet to be a major UML breakthrough for SoC design. However, with the arrival of a new generation of customizable UML tools based on the principles of model-driven architecture (MDA), we expect a major impact in this area, too.

In the field of model-based verification (also called model-based testing in the software and automotive systems domain), for instance, some UML tools already support testbench specification and code generation. One such tool is Telelogic’s Tau, which generates validation sequences in the TTCN-3 language from sequence diagrams. Other tools like dSPACE’s AutomationDesk employ activity diagrams for test descriptions and test script generation.

Typical usage patterns of UML subsets in the field of behavioral SoC designs exploit state-machine, activity, and sequence diagrams in combination with use cases. I-Logix pioneered the generation of synthesizable VHDL from state charts, the precursor of state-machine diagrams in UML. More recent work also considers the use of state-machine and activity diagrams when compiled to VHDL, SystemC, and Handel-C for simulation and synthesis. In that context, the electronics industry (e.g., Fujitsu, NEC, and STMicroelectronics) investigated several case studies and hardware/software co-design methodologies based on UML (such as ACES from NEC Labs).

A key strength of UML is its ability to be extended with domain-specific customizations—the so-called profiles. A prominent example of an existing profile relevant in the embedded-system domain is the UML profile for schedulability, performance, and time (SPT). This is expected to be improved and extended by the upcoming Modeling and Analysis of Real-Time and Embedded systems (MARTE) profile.

Of particular interest for SoC design is the submitted UML extension profile for SoC \[4\], as well as the Systems Modeling Language (SysML) \[5\]. The SoC profile targets SystemC-oriented applications. SysML, which extends UML for general systems engineering, deals with continuous quantities, requirements, and physical assemblies such as IP blocks.

In order for a profile to be used for real applications, it must be:

Easy to use by domain experts; preferably, it should come with application guidelines

Formalized as a machine-readable standard format given by a so-called metamodel.

Several tools are already available, which take such metamodels for their configuration. Some of those tool suites, such as Accelerated Technology's Bridgepoint and ARTiSAN Software's Real-Time Studio, also support customizable code generation.

All in all, we see an emerging interest in UML’s application for SoC specification and analysis. In fact, several significant and ongoing efforts are focused on customizing UML toward SoC design. With the emergence of methodologies and the availability of a first set of dedicated tools, UML has great potential as a complement to current C++-based languages for SoC design. We also feel that SysML offers strong opportunities as a specification language beyond transaction-level and electronic system-level modeling.

An additional potential lies in UML’s application for architectural, component, and interface description. Intellectual property (IP) integration and packaging, such as that being proposed by the SPIRIT Consortium \[6\], can become easier by inheriting some of UML’s advanced object-oriented concepts. To this end, we realize that the current UML standard together with SysML is a complex framework of highly intertwined concepts. As a result, we definitely see a clear need for education before the SoC designer can benefit from UML and its rich set of concepts.

\[1\] L. Lavagno and W. Mueller. UML for SoC Design Workshop at DAC’05, Anaheim, CA, USA, June 2005, http://www.c-lab.de/uml-soc
\[2\] G. Martin and W. Mueller. UML for SoC Design Workshop at DAC’04, San Diego, CA, USA, June 2004.
\[3\] G. Martin and W. Mueller (eds.). UML for SoC Design, Springer, June 2005.
\[4\] OMG. UML Extension Profile for SoC. ptc/06-04-18, April 2006.
\[5\] SysML Merge Team. Systems Modeling Language Specification Version 1.0 Draft. OMG document ad/2006-03-01. March 2006.
\[6\] Spirit Consortium, http://www.spiritconsortium.org.

Luciano Lavagno , a research scientist at Cadence Berkeley Labs, has worked on several projects in the system-level and digital implementation spaces.

Wolfgang Mueller heads the advanced design technologies group at C-LAB, a joint R&D institute of Paderborn University and Siemens.

Note: The third annual UML-SoC’06 Workshop will be held during the 43rd Design Automation Conference (DAC) Sunday, July 23, at the Moscone Center in San Francisco. For more information regarding registration and the complete program, visit the DAC website at www.dac.com or the UML workshop website at www.c-lab.de/uml-soc/ .

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