1. Select an FPGA with an ASIC-like power profile. That means no inrush power, no boot-up configuration power, ultra-low standby power (especially over extended temperature ranges), and low dynamic power. Low-power and secure in-system programmability allow secure design modifications and field upgrades.
2. Look for single-chip, small-form-factor (portable-friendly) FPGAs. The ASIC-like form factor is the smallest footprint available for an FPGA solution. No configuration PROM, brownout detection, clock management, or supply-sequencing chip is required, minimizing system power consumption.
3. Look for low power even at million-gate densities and at high temperature. SRAM FPGAs are power-hungry in standby and active modes and at high-temperature operation. Use flash FPGAs, which offer orders-of-magnitude lower power in standby and active modes, across temperatures.
4. Extend battery life with low-power modes. The availability of low-power modes further reduces total system power when the system is idle. Easy-to-use modes in low-power flash FPGAs can reduce current consumption to as low as 5 µW in Flash*Freeze mode.
5. Use an FPGA that can manage system power. Low-power, mixed-signal FPGAs and ARM-enabled flash FPGAs enable system power management and power islands by monitoring and controlling the power consumption of the battery and other components to achieve system power efficiency.
6. Optimize for dynamic power. Look for vendors that support software tool optimization for low-power layout. Use FPGAs that offer reduced core voltage and can instantly be switched in and out of low-power modes.
7. Use flash memory save and restore capabilities. FPGA on-board user flash memory can enable the power-down and power-off modes of operation.
8. Use Level 0 live-at-power-up (LAPU) nonvolatile FPGAs, which simplify lowpower system design. Level 0 LAPU FPGAs quickly power up and restore the system state from sleep mode without the need to reload the configuration. Entering and exiting Flash*Freeze mode is quick and easy, which helps reduce power consumption and increase usability.
9. Reduce total system power by using devices with higher system integration. Look for programmable logic that integrates power FET control and supports simplified sleep and standby power modes as low as 5 µW. Additional integration of clocking resources, the voltage regulator, and the analog-to-digital converter removes parts from the board and reduces total current consumption.
10. Use enable flip-flops and regional clock resources. Limit dynamic power consumption by utilizing FPGA power-friendly architectures that allow the use of segmented clocks and enable flip-flops. Also use lowpower, high-performance serial connections such as low-voltage differential signaling (LVDS) with double-data-rate (DDR) registers to minimize I/O power consumption.