After several years of trying to perfect the technology of 3D IC packaging, the stage is now set for fruitful results. In fact, several IC industry experts predict that this will be the year 3D ICs make their commercial debut. Refinements in through-silicon via (TSV) interconnect technology will be key enablers.
Some 2.5D chips have been commercially available, and field-programmable gate arrays (FPGAs) are making a competitive push to 3D architectures. But most semiconductor IC experts believe that making devices and packaging them using 3D ICs with TSV technology is the ultimate goal and the “state of the art.”
This is supported by developments coming out of semiconductor companies like Samsung, Intel, ST-Ericsson (a joint venture between STMicroelectronics and Ericsson), and IBM. Another indicator is that the pace of 3D IC activity among companies, research centers, universities, and standards organizations has been frenetic (see “A Host Of 3D IC Collaborations And Standardization Efforts Emerging” at electronicdesign.com).
IBM has been mass-producing full-fledged 3D ICs for high-volume mobile consumer electronics devices using low-density TSVs. But the company has kept this work under wraps until recently when it announced 3D IC technology at last month’s IEEE International Electron Devices Meeting (IEDM). Micron Technology Inc. will use IBM’s advanced TSV technology in its Hybrid Memory Cube (HMC), which is expected to achieve speeds 15 times faster than today’s technology in a 90% smaller package (Fig. 1). The device will be manufactured at IBM’s fabrication facility in East Fishkill, N.Y., using IBM’s 32-nm high-K metal-gate process.
IBM’s approach so far has been to use low-density TSVs. The company has identified one major hurdle, the need for solving the overheating problem in 3D ICs with TSVs. To solve this, IBM is working closely with 3M, which is looking at making a “designer” material that fits between stacked dice and is an electrical insulator, but is also more thermally conductive than silicon.
According to IBM, HMC combines high-performance logic with Micron’s state-of-the-art DRAM technology. Prototypes will feature bandwidths of 128 Gbytes/s, while state-of-the-art capabilities offer 12.5 Gbytes/s. It also requires 70% less energy to transfer data in a much smaller form factor.
The HMC 3D technology, IBM says, will enable a new generation of performance in applications ranging from large-scale networking and high-performance computing to industrial automation and eventually computer products.
“This is a milestone in the industry’s move to 3D semiconductor manufacturing,” says Subu Iyer, IBM Fellow.
“It is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiency,” agrees Robert Feurle, vice president of DRAM marketing for Micron.
Just when such a product will become available is not clear, but most experts believe it may become available sometime this year or next. They also caution that many other issues need a solution, not just thermal management. Even IBM agrees with that assessment.
“You’re not going to win the 3D IC performance battle if you rely solely on materials, or on chip architecture, or networking, or software and integration. You must use all these resources together at the most holistic level,” explains Bernard Meyerson, vice president of research at IBM’s facility in Armonk, N.Y.
Robert Patti, chief technology officer and VP of design engineering at Tezzaron Semiconductor, concurs with this view. He points out that using normal 2D tool flow software—even refined versions for 3D ICs with TSVs—is not enough.
Tezzaron points to a prototype IC it is building with several partners that is the result of using advanced 3D tools and software. The demonstration device contains an ARM processor stack, an off-the-shelf FPGA die, and a DRAM memory stack, all assembled onto an active silicon circuit board that functions as an interposer (Fig. 2).
Wafer-Level and Chip-Scale Packaging
To satisfy the needs of today’s mass-market mobile devices, which require the integration of more functions in a smaller form factor like mobile phones and tablets, package-on-package (PoP) technology using flip-chip, chip-scale, and wafer-scale packaging is being used. PoP involves stacking several packaged devices like memory and application-specific processors atop one another within a larger package.
Amkor, for example, uses through-mold vias and fine-pitch flip-chip interconnects with copper pillar bumps to deliver next-generation high-density PoPs. The company is well aware of the need for 3D ICs with TSVs and is actively working on this technology, focusing on developing solutions for the back end of TSV processing.
Flip-chip, wafer-level, and wafer-bump processes are satisfying present market needs until TSVs are perfected for 3D ICs.
“These processes cater to the most demanding needs of mobile and consumer devices,” agrees Wan Choong Hoe, executive vice president and chief operating officer of STATS ChipPAC. The company provides back-end fully integrated packaging and testing solutions that bring products to the market faster, such as package design, bump, probe, assembly, test, and distribution services.
A recent arrival on the 3D IC wafer-level chip-scale package (WLCSP) front, Deca Technologies, promises to slash heretofore unsolvable packaging costs for 3D ICs drastically with a series of WLCSP products that offer speed, low cost, and flexibility options not available with present 3D ICs using TSVs. Deca expects to be able to go from the design to the manufacturing step in less than an hour and says it will have products on the market sometime this year or next.
IMEC researchers have developed a WLP technology for packaging microelectromechanical-systems (MEMS) devices. WLP is essential for MEMS devices to protect the fragile MEMS structure from the hazards of the back end of the assembly process as well as the device’s operating environment. Technically, MEMS devices are 3D ICs due to the mechanical nature of their operation, which requires space for the sensing element to work.
This comes after an announcement by SUSS MicroTec that it is partnering with SVTC Technologies by supplying the latter with alignment and bonding equipment for MEMS 3D IC package development. They will focus on new WLP processes and solutions.
IMEC has demonstrated the fabrication of extremely small sealed cavities (less than 1 pL in volume), directly on 200-mm silicon wafers using thin-film nanoporous alumina membranes (Fig. 3). The thin-film technology bolsters the device’s strength and the package’s air-tight hermeticity.
To remove the sacrificial layer and to form the microcavity between the MEMS element and the capping layer, lithographically defined release holes are made. A cylindrical 2- to 3-µm thin free-standing cap layer (15 to 20 µm in diameter) is used whose nanopores serve as release etch holes to keep the package’s sealing materials from leaking into the cavity underneath.
One of the leaders producing environmentally resistant MEMS packaging, ePack, employs a robust packaging process in an oven-controlled vacuum and hermetically sealed environment of 200°C to 400°C. The MEMS device is equipped with a cap and a platform for thermal and vibration isolation. Heaters and temperature sensors are used on the platform (Fig. 4).
Vacuum packaging and process cleanliness are extremely important for MEMS devices used in military, industrial, and medical environments.
“Achieving high levels of vacuum is a very challenging task,” explains Jay Mitchell, CEO and cofounder of ePack along with Sangwoo Lee. He cites vacuum levels needed to make their MEMS device on the order of 7.6 mTorr, which is equivalent to one one-millionth of an atmosphere, and more than 100 monolayers of water vapor in a cleanroom. “It is very important to design your packaging solution along with your sensor. This should not be an afterthought,” he says.
Mary Ann Maher, founder of SoftMEMS LLC, stresses the importance of using software co-design principles for MEMS-based products. She points out that software can be used to validate new package concepts where the TSVs in MEMS devices are simulated to determine the characteristics of the via and to find fabrication errors. The simulator emulates the buildup of materials used to construct the via.
Thermo-mechanical simulations are performed as each layer is deposited to determine stress and temperature behavior (Fig. 5). Electromagnetic simulations are used to determine the via’s electrical behavior.
FPGAs at 2.5D?
FPGAs are making progress in using silicon TSVs for 3D ICs, particularly in a relaxed-geometry mixed-signal die, where TSVs are on a 50-µm pitch or greater and there are no concerns for modeling mutual-inductance or even capacitive coupling effects. Many in the semiconductor industry refer to so-called 3D FPGA ICs as 2.5D ICs.
Xilinx’s Virtex-7 2000T FPGA packs 6.8 billion transistors using four chip slices and links them together using a silicon interposer layer, all without the need for I/O buffers (Fig. 6).
There are no logic or interface elements in the TSVs. TSMC is making the silicon interposers, which allow the redistribution of the FPGA interconnections using TSVs that mate to copper balls on a substrate package that uses a controlled-collapse chip connection (C4).
Not everyone is convinced the path to 3D silicon ICs rests on developing TSVs. Zvi Or-Bach, president and CEO of startup MonolithicIC 3D Inc., argues that high-density monolithic 3D ICs are possible without the need for TSVs. His patented IP Ion-Cut method uses crystalline silicon that can be formed above copper wiring, which can be useful for making 3D logic, memory, FPGAs, and electro-optic functions, at 1000 times higher densities than TSVs (Fig. 7).
Other materials besides silicon interposers, like glass and carbon nanotube interposers, are also being investigated in the search for the ideal 3D TSV solution. Tests on glass interposers are underway at Taiwan Semiconductor Manufacturing Corp. (TSMC) and the Georgia Institute of Technology.