By temporarily storing data in multiple channels between the input/output terminals and the memory cells, NEC's Virtual Channel memory technology is said to enhance the latency and throughput of existing DRAM architectures. The firm's first 64-Mbit Virtual Channel synchronous DRAMs are available in three organizations: the 8-Mb-word x 4-bit x 2-bank PD4565421; the 4-Mb-word x 8-bit x 2-bank PD4565821; and the 2-Mbit-word x 16-bit x 2-bank PD4565161.The ICs are housed in 54-pin, 400-mil, TSOP-II packages with pin layout and a LVTTL interface that's compatible with existing 64-Mbit SDRAMs. Thus, there's no need for board-level changes. They offer data throughput of up to 143 MHz with read latency at two clock cycles, which represents speed and efficiency that's difficult to achieve with conventional SDRAM architectures. Samples are available now with volume production slated for October.
Company: NEC ELECTRONICS INC.
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