Wireless Systems Design

Accelerator Emphasizes Memory Interface

This Platform Speeds Java Software Execution By Integrating A Combination Memory On A Multichip Package.

Two important trends are changing the landscape for cellular-handset designs. First, there's the merging of application processors and Flash memory onto a combined package. These packages, which are sometimes called systems-in-a-package (SIPs), usually consist of several die. These die are stacked and electrically bonded within a single multichip package (MCP).

The second landscape-altering trend is the growing acceptance of Java. Java is becoming the software platform of choice for many handset designers and carriers. This year, analysts believe that as many as 150 million of the handsets sold will be Java enabled. That number equals a third of the 400 to 450 million handsets that are expected to sell.

To simultaneously take advantage of both of these trends, NanoAmp Solutions, Inc. has developed a Java hardware accelerator. This accelerator is actually the third die in a widely used SRAM/Flash multichip package. It is officially known as the Memory Oriented Coprocessor Accelerator for the Java platform, or MOCA-J. This device will address the Java performance issue by offering an accelerator that is integrated with existing Flash memory (see figure).

In addition to the more efficient use of circuit-board space offered by this multichip design, the MOCA-J approach offers a faster time to market. It also claims to be one of the lowest-cost Java-acceleration solutions for wireless handsets, PDAs, and mobile devices. NanoAmp estimates that the MOCA-J combination chips can be made for under a $4 premium over existing memory devices.

As an added benefit, this combination design will interface onto a circuit board just like a standard combination-memory MCP. It also boasts compatibility with any host handset-baseband chip set, system-on-a-chip (SoC), or microprocessor. Like other high-performance Java accelerators, the MOCA-J will not demand any modification of the underlying real-time operating system (RTOS) or legacy-application software.

One of the characteristic features of the MOCA-J platform is its capability to accelerate the execution of Java byte-code instruction. This means fewer clock cycles per instruction, which should extend the device's battery life. In fact, it promises to reduce consumption by up to 90% compared to other Java approaches.

With the 104-MHz NanoAmp core, the company believes that its MOCA-J architecture also can boost the performance of handsets. Using Java2 Micro Edition (J2ME), it can increase handset operation to up to 20 times faster than they would be with a software Java virtual machine. They can be six times faster than handsets that use ARM Jazelle Java-acceleration technology. Such high speed can be achieved because the MOCA-J design process shares the memory bus with the MCP. It can therefore execute Java instruction directly within the MCP.

Several flexible-I/O-interface options are available in the MOCA-J architecture. A modified version of a typical 16-b asynchronous memory interface serves as the interface between the NanoAmp coprocessor and the cellular handset's host processor. Memory interfaces support SRAM, Pseudo SRAM (PSRAM), and Flash technology. The various I/O-interfacing options are selectable using a chip-enabled or high-order address signal. The architecture supports the common voltage ranges of 1.8 and 3.0 V.

The NanoAmp core is a 32-b coprocessor that runs at up to 104 MHz with integrated instruction, data, and Java-virtual-machine caches. In a single cycle, it can execute most Java byte codes. These codes are the compiled Java source-code instructions.

Thanks to the three Level-1 (L1) caches built directly into the core, execution occurs at full clock speed with no wait states. The L1 cache, also known as the primary cache, is built directly into the processor.

The future versions of the MOCA-J architecture will include other logic functions, such as security or multimedia accelerators. Silicon based on the architecture is being sampled now. The architecture is scheduled for volume production in the second quarter of this year.

NanoAmp Solutions, Inc.
1982-B Zanker Rd., San Jose, CA 95112; (408) 573-8878, FAX: (408) 573-8877, www.nanoamp.com.

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