PCB layout is getting tougher with larger BGA chips. They require multilayer boards with more complex designs requiring many layers. Simplifying PCB design and reducing the number of required layers reduces system cost and improves reliability. The challenge is to deliver these advantages without increasing complexity.
I had a chance to talk with Keven Coates, Senior Systems Engineer, about Texas Instruments' Via Channel technology. This is a methodology for designing BGA ball layout to simplify PCB design using these chips.
Wong: What is your role at Texas Instruments (TI)?
Coates: My job is to design processor packages. Since I have experience in the design and layout of printed circuit boards (PCB), part of my mission at TI is to make sure our new products take the PCB cost and design into account. I think too many semiconductor companies may not have been considering the difficulty and expense their customers face when trying to use some of the new small pitch parts on the market today.
Wong: What do you see as the future for ball grid array (BGA) packages?
Coates: Smaller and smaller pitches. This will progress slowly since PCB fabrication technologies have not kept pace with silicon integration and semiconductor companies are starting to see that.
From a semiconductor company point of view, it makes sense to put silicon in the smallest package possible, which would mean 0.4 mm pitch or even smaller because small packages reduce our costs, so we can sell the part cheaper. However, we realize a 0.4 mm pitch package is not going to be compatible with a low cost PCB, so we’ve got to take a different approach.
Since most of TI’s customers are very cost conscious, TI takes a system cost perspective when choosing processor packages, and customers have reacted very positively to this.
Wong: What are some solutions TI has used to make low cost PCBs possible even with the newer, smaller pitches?
Coates: TI created Via Channel™ technology. It’s a method of designing a BGA with select areas of depopulated balls to enable easy PCB routing and cheaper PCB fabrication technologies to be used.
Wong: How does Via Channel technology work?
Coates: Figure 1 shows the upper left portion of a typical full array BGA route (since the other portions of the array will route mirrored to this one).
Notice how the first layer (grey traces) are close together, that means the top layer has good density. The second layer (red traces) is the same, but once you get into the third signal layer (maroon), the density drops off sharply because the vias used to get signals to the second layer are in the way.
Since the maroon (third layer) and yellow (fourth layer) traces are farther apart, this means these layers are not helping get the signals out as much as the first two layers since the trace density on these layers is sparse. This is because the vias (shown in purple) are acting like a dam, impeding the flow of traces in the area much like the lid on a salt shaker slows the flow of salt out of the shaker.
What if we could rearrange the vias so that we could have bigger holes in the “salt shaker” and at the same time use bigger vias to reduce PCB cost? This would enable more traces to get out from under the BGA array on each layer, which would reduce the number of layers required to get the signals out, and we’d have a cheaper PCB.
Figure 2 is an example of the Via Channel concept (second signal layer shown). The end result for this example is that this 0.65mm pitch BGA design (432 balls) allowed all the signals to escape on just two signal layers with larger and cheaper PCB feature sizes than was possible on the 0.8mm pitch BGA.
This shows how the vias are now placed in areas where the balls have been removed, and they’re in a different pattern because of this.
Since the area for the vias is cleared of balls, any size via can be designed for when designing the package. Now a large 20 mil diameter through-hole via can be used with a 0.65mm pitch array for example, or even a 0.5mm pitch array if the package is designed that way. The result is that with a Via Channel package, smaller BGA pitches no longer mean higher PCB costs.
Because the vias are arranged in rows from the inside of the array to the outside instead of in concentric squares (as in the first example), the traces flow much better in between them. The trace density on every signal layer is increased to the point of needing only two signal layers in most cases.
With this technology, the package requires less layers and even 0.65mm and smaller pitch parts can route with low cost 1.0mm pitch PCB rules.
Since we have to remove balls to make this work, the result is less dense than the full array in the same pitch. The good news is that we can now reduce pitch but use the same PCB rules, so we can more than make up for the missing balls.
The part is now smaller, and the cost of the PCB and part is reduced! Here’s a comparison of a 400 pin part.
0.8mm Standard Pitch versus 0.65mm Via Channel Pitch
|Comparison||Standard 0.8mm pitch||0.65mm p. w/Via Channels|
|Min Trace||4 mils||4 mils|
|Min Space||4 mils||4 mils|
|Via Diameter||18 mils||20 mils|
17mm by 17mm
16mm by 16mm
|Reduction from 0.8mm||--||11%|
Wong: What ball pitches are used with this technology?
Coates: We typically use 0.65mm pitch since the sizes work out nicely with our PCB design targets. In the future, we could use 0.5mm pitch, or any other pitch and design the part for whatever size via and trace we wanted, still targeting low cost PCB rules.
This is because the ball pitch no longer dictates board cost. In fact, smaller pitches work better with this technology because more of the array is filled with balls. We’ve also got more possibilities for ball placement with smaller pitches. But whether we use 0.5mm pitch or 0.8mm pitch, the PCB cost is the same because the design targets we choose are such that any of our customers can stay in the mainstream consumer electronics production via and trace width sizes.
Wong: Are there any downsides to this technology?
Coates: There is a lot of package design work required early in the silicon design process. We’ve got to know how a part will route on the PCB even before the silicon floor plan is done. Really, this is the way it should always be done (up front), this just makes it more important.
In come cases, this isn’t the right technology for customers designing the absolute smallest product, such as cell phones, since it’s not as dense as a full array in the tiny pitches customers usually use However, for customers more concerned with PCB cost, this holds many benefits since it eases their design and reduces their costs greatly compared with small pitch full arrays.
Wong: How many TI chips use this technology?
Coates: TI has five main processor lines that offer a Via Channel package, and we’re planning on making at least one Via Channel package available in most new processor lines we build.
Wong: How have customers reacted to this new TI Via Channel package technology?
Coates: We’ve received very positive feedback. For example, one customer responded that for the first time, he could see that the chip was actually designed to be put on a PCB. Customers have really enjoyed the freedom this technology gives them.