Blue Whale Surfaces With Chip Size Wafer-Scale Packaging For Handheld SoCs

Members of the Blue Whale Consortium, a project funded by the Information Society Technologies (IST) Programme of the Fifth Framework Programme of the EC, have announced in Munich the successful completion of its mission to develop high-performance, cost-effective chip size wafer-scale packaging for System-on-Chips (SoC) for handheld devices.

Contrary to existing single chip packaging or system-in-package, the Consortium members demonstrated a chip size wafer-level packaging technology to achieve “true die size” packaging and, consequently, the highest miniaturisation possible. Packaging has a major effect on the final size of the system as well as on the system’s electrical performance.

The Consortium was created in 2002 with the objective of demonstrating wafer scale packaging concepts for RF SoC and for power devices, as well as to develop equipment for a wafer balling process. Consortium members include Philips Applied Technologies, which also served as the project manager; DEK International (UK), Dimes, a subsidiary of Delft University of Technology (the Netherlands), Shellcase (Israel), and TU Berlin (Germany).

SoC solutions, which entail integrating several system functions into one piece of silicon (monolithic integration), avoid the problem of having too high a ratio of the semiconductor area being used for interconnects.

“System-on-Chip is expected to evolve rapidly in the coming years,” explained Dr. Co van Veen, who led Philips Applied Technologies’ involvement in the consortium. “By combining a RFCMOS - IC, with mixed functionality potential, and wafer level packaging, we showed that it is possible to achieve a 90% reduction in occupied area on the printed circuit board, compared with the standard QFP solution.”

Philips Applied Technologies focused on the specification, design and the developments of the key technologies for packaging of RF SoC and power transistors. The package was developed in cooperation with Shellcase and the power transistor package was developed in co-operation with DIMES and TU-Berlin. DEK focused on developing equipment for the application of solder balls on wafers. The company used two approaches, including stenciling prefabricated solid spheres, and has already commercialised the equipment it developed during the project.

Dimes provided the Consortium with electronic modeling studies and developed strategies for wafer testing of wafer-scale packages.

Together with Philips Applied Technologies, Shellcase designed and developed packaging concepts for RF-CMOS SoC, including modules with optional component stacking on the back. It also provided input for the development for the wafer balling equipment. Shellcase’s contribution of wafer level chip size packaging, which results in true die size packaging, helped to maximise the level of miniaturisation achieved.

TU Berlin focused on thermal and thermo-mechanical modeling for the wafer-scale packages. This company also worked with Philips Applied Technologies on 3D Electroless redistribution technologies for power transistors, employing Via-in-Via concepts. TU Berlin also collaborated closely with DEK on the development of advanced balling processes of up to 400mm pitch.

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