The pressure to squeeze more power from a conventional MOSFET has prompted Fairchild Semiconductor to improve the current-handling capability of the popular wireless SOIC package. Specifically, the company hopes to attain the thermal performance and current-carrying ability of a larger TO-263 or D2PAK package from the footprint of the industry-standard SO-8 package.
With the FDS7064A n-channel MOSFET, engineers have improved the wireless SOIC by extending Fairchild's solder-bump technology. The continuous leadframe is attached to the die, which has been bumped with solder balls at the wafer level. Consequently, the bottom drain leads normally found in conventional SOICs are eliminated—hence the term, "bottomless."
The company says that this technique provides unsurpassed RDS(ON) from an SOIC footprint. The FDS7064A's maximum on-resistance is rated at 6 mΩ at a VGS of 4.5 V. Designers eliminated the wirebonds and directly mounted a pc-board heatsink on the solderable backside of the MOSFET die. As a result, the bottomless technology slashes junction-to-case thermal resistance from 25°C/W—typical in conventional SOICs—to 1°C/W.
The source leads also are well coupled to the MOSFET source to further improve the device's thermal resistance. The bottomless package can then handle 50% more current than the same die packaged in a conventional SO-8, Fairchild says. The continuous drain current for the FDS7064A is rated at 20 A with a 30-V drain-source breakdown voltage.
Sampling now, the MOSFETs in bottomless packages will go into volume production late in the third quarter. In 10,000-piece quantities, the FDS7064A is priced at $0.95 each.
Fairchild Semiconductor, Discrete Power and Signal Technologies, 1322 Crossman Ave., mail stop D-100, Sunnyvale, CA 94089; (888) 522-5372; www.fairchildsemi.com.
