I don't normally write about wafers and die sales because these kind of transactions tend to be very involved and typically very expensive. This is compared with conventional chips sales where off-the-shelf components are simply ordered and the amounts can be very small up to very large quantities.
Most companies are set up to take advantage of conventional packages that are mounted on PCBs (printed circuit boards). Footprints are standard and soldering is a matter of standards. Dealing with a raw die tends to be significantly more difficult and it often involves significantly more variables that packaging often hides.
The payoff of dealing with a raw die ranges from use in space constrained applications to multichip packaging. The downside, until now, has been significantly higher expensive, a high start up cost, large minimum commitments and dealing with custom designs. These tend to be of less consequence if the volumes are high but it has typically limited the use of raw die when smaller quantities are involved. Vendors do not typically support this approach if it is not economical for them.
Silicon Labs looks to change this situation or at least to significantly lower the entry bar. It is making its standard product line of 8- and 32-bit microcontrollers available in minimum order quantities (MOQ) as small as a single wafer (Fig. 1). That is still a lot of dies so it is not an option for half a dozen units but it does mean designers can get raw die when they are not looking at quantities like a million units or more.
Silicon Labs has a number of precision analog microcontrollers including ones based on the 8051 (see Integrated DC-DC Buck Converter Reduces 8-bit Power Requirements) as well as the latest SiM series based on the 32-bit Arm Cortex-M3 (see Precision Analog 32-bit Micro Uses A Crossbar Interconnect).
The new sales program provides designers with the standard footprints for these chips along with detailed die-specific data sheets. The die are fully tested including the analog and digital peripherals. Failure analysis (FA) results are available for a wafer that has to be returned but this is for the exception. Silicon Labs supports factory programming and serialization so die can be utilized immediately. The die test flow is typical with Silicon Labs providing a wafer map or marking bad die.
The lead time is as low as 2 weeks less than the standard lead time with a forecast. The customer is responsible for dicing wafers and then processing the die. Because of wafer yield variations, the actual number of die per wafer will vary but the average yield will be well known.
The possibilities for raw die design are numerous. The can be used for space constrained form factors such as Multi-SIM cards, RFID, and optical modules.
The use of raw die is not for all designers, even those needing a significant number of devices. Likewise, designing and deploying a system that incorporates raw die is not a simple task, at least compared to using packaged devices. Still, Silicon Labs is significantly lowering the bar for designers and opening this possibility to many more developers. It is also a scalable solution since getting more wafers is simply an additional order.