Electronic Design

Cash In Your Chips By Going Multicore

It's time to place your bets. What's going to create the most buzz this year? Heavy odds say it will be multi-core processors and multi-core system-on-a-chip (SoC) solutions. Some multi-core products will be implemented as standard products, while others will be crafted as application-specific standard products (ASSPs). Still other implementations will be full-custom application-specific ICs (ASICs) specific to a single customer.

It's getting harder to maintain the power envelope in which commodity and server CPUs must operate due to ever-increasing clock frequencies. By using two lower-speed CPU cores on one chip, however, dual-core processors from Intel and AMD can deliver better throughput while consuming less power than a single higher-speed core.

In addition to dual cores, Intel's hyper-threading technology—used on both single-core CPUs and the dual-core Pentium Extreme Edition—enables the dual-core chip to run two instruction threads on each of its two cores. As a result, systems can run four simultaneous programs.

Even the PowerPC is moving to dual cores. Used by Apple Computer in many desktop and portable systems, the popular Altivec processor soon will have a more highly integrated dual-core cousin, the MPC8641D. Optimized for network-related applications, each of its two full e600 PowerPC cores will boast a 1-Mbyte L2 cache that packs error-checking and correction.

The MPC8641D also will feature the Altivec vector-processor extensions. The chip integrates a system controller and a PowerQUICC network subsystem that includes four Gigabit Ethernet ports, serial RapidIO ports, and a PCI Express interface.

Dual-core CPUs are just the starting point. Intel recently revealed a roadmap with at least one quad-core design on the drawing boards. And Sun Microsystems' latest UltraSPARC CPU, code-named Niagra, offers eight cores. Targeting servers and blade servers, each one of Niagra's cores can run four instruction threads for 32 instruction streams overall, as if 32 processors were available to the operating system.

Multi-core processors aren't new, especially in the embedded market. Network processors have taken advantage of single-chip multiprocessor solutions for years. But it's now possible to integrate over a billion transistors on one chip. Therefore, designers can implement much more complex cores than previously possible, as well as provide substantial multilevel caches and other resources. The final result will be chips with supercomputer-class performance.

In ASSPs and ASICs, multi-core CPUs are making their way from the industrial embedded space into mass-market consumer products. For example, Microsoft uses a custom triple-core PowerPC-based CPU as the heart of its Xbox 360.

Partnered with IBM and Toshiba, Sony developed the multi-core Cell processor. It combines a PowerPC core that serves as a system controller with eight identical compute engines operating in parallel to handle graphics and other computation-intensive applications. The Cell processor also will find homes in non-gaming applications. Mercury

Computer Systems is developing several compute platforms based on arrays of Cell processor chips. The first is a blade server based on two Cell processors (see the figure). The latest system, the Turismo, delivers 800 GFLOPS in a 600-in.3 footprint. Multiple Turismo boxes can be combined to provide supercomputing solutions.

ASICs PUT IT ALL TOGETHER
ASIC vendors, fabless chip design houses, and OEMs must rely on every aspect of semiconductor technology to craft such highly integrated solutions. These companies require advanced processes and metallization schemes to integrate and interconnect the billion or so transistors; new transistor structures to achieve faster switching times and lower power drains; IP libraries to reduce design time; and design tools to help assemble, lay out, and verify the design.

AMI Semiconductors, IBM, and LSI Logic, for example, provide full ASIC implementation services. They offer a one-stop solution with libraries, design-tool flows, and full chip manufacturing from silicon to packaging. TSMC, UMC, Chartered Semiconductor, Silterra, and SMIC provide foundry services that come close to the services supplied by ASIC vendors, but they don't directly offer design services. Large OEMs, including Fujitsu, Freescale, and Toshiba, provide ASIC services much like those of ASIC suppliers. Or, they can offer foundry services.

Many of these companies have chip-fabrication services using 90-nm process rules. A few offer design kits for customers to develop chips based on 65-nm process rules. Chartered, which licensed IBM's high-performance silicon-insulator (SOI) technology, offers that process in its foundry. Freescale uses its SOI manufacturing capability for standard products and as a resource for ASIC/ foundry customers.

The high cost of developing an ASIC in a 90-nm process, typically estimated between $15 million and $20 million, makes many companies think twice about whether a full-custom solution is economically viable. When a design doesn't work properly after initial fabrication, the cost of fixing errors and redoing the masks, plus the time lost to prefabricate the chip, bloats overall development time and cost.

TRIMMING HIGH ASIC COSTS
To counter spiraling costs, vendors are developing partially remanufactured solutions called structured and platform ASICs. Fundamentally, these solutions leverage the basic precept of the gate array, but they offer much more as a starting point. Typical resources offered on the structured and platform chips include blocks of RAM, phase-locked loops, high-speed I/O buffers, and multigigabit serializer/ deserializer ports.

Today, most structured and platform offerings are implemented with 130-nm processes. But a few companies, such as LSI Logic and Fujitsu, squeeze the design rules down to 110 and 90 nm, respectively, for their highest-performance offerings.

Because the silicon is remanufactured, and the pre-integrated functions are verified, designers need only create the metal interconnect definition for their circuit functions. Then, the final few metal masks can be prepared to complete the manufacturing process. This considerably lowers the final nonrecurring-engineering costs for design verification and mask creation. It also shortens the turnaround time from design handoff to samples.

But the chips aren't custom-crafted, so they tend to be slightly larger than a potential full-custom implementation of the same logic—and perhaps, not quite as fast. The larger chip size often translates into a higher per-chip cost than a custom ASIC, especially if the ASIC will be produced in large quantities.

As the cost of developing a full ASIC continues to soar, so does the popularity of structured and platform solutions. Over two dozen large and small companies compete in this market. They offer solutions that use customization schemes ranging from direct electron-beam patterning for mask-less final configuration to about five levels of metallization to configure logic fabrics based on a fine-grained logic building block.

The broadest set of platform ASIC offerings continues to come from LSI Logic, with its nearly two dozen configurations. These chips also make a good transition solution for many designs initially implemented in an FPGA, which are now ready for some level of volume manufacturing.

LIBRARY UPDATES CRITICAL
Key to the timely deployment of any ASSP or ASIC is the ability to exploit available IP that will reduce the SoC's design time. To encourage IP use, ASIC suppliers and foundries continue to build their IP libraries and partnerships with various IP suppliers to further expand the building-block options.

CPU cores ranging from 8-bit controllers (e.g., 8051s) to 32-bit architectures (e.g., ARM7 and ARM9), as well as the ARC and Tensilica cores, have been available. But expect many next-generation cores to significantly improve performance. Some of these cores include ARM's ARM11 and Cortex-A8, as well as enhanced CPU cores from ARC and Tensilica. They will sate the demand for ever-higher throughput.

Upcoming blocks of IP include DDR2 memory controllers, H.264 video encode/ decode blocks, PCI Express interfaces, and other blocks targeting the audio/ video and consumer markets.

Design support for cores comes in the form of standard buses and standardized logic interfaces (sometimes called wrappers). Such support has made its way through standard organizations such as the VSI Alliance, the Silicon Integration Initiative, and the European Electronic Chips and Systems Design Initiative. These groups are hard at work developing SoC, IP, and reuse standards, which will ultimately enhance the productivity of SoC designers.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish