Electronic Design

Chip-Scale Packaging Is Ready For Prime Time

Flash back to 1981. Plastic surface-mount packaging moved from the lab into the marketplace. Philips pushed the now industry-standard SO package while the Japanese created their own footprints around a very similar concept. Adoption in the Americas was slow, however. Some blamed the lack of a driver, such as portable consumer products that had already moved overseas. But I also remember hearing about a lot of foot dragging. "This tiny stuff is hard to handle in manufacturing," or "Through-hole is running just fine, thank you. It has a lot of life left in it."

Flash forward to 2001. An exciting new microminiature package, the chip-scale package (CSP), arrives and makes the SO look hunky in comparison. Cell phones from leading manufacturers in Europe will soon be sporting CSPs. They have already been embraced by Japan in numerous portable handheld devices. Déjà vu? Let's look at what CSPs have to offer and explode a few myths.

All three types—substrate, leadframe, and wafer-scale CSPs—pack more functions into less space than any previous package. They're thin (typically 1 mm) and devoid of the space-hungry pins that protrude from conventional packages, making them ideal for ultra-small and ultra-thin boards mandated by tomorrow's handheld devices. They're available in pin counts ranging from four to 48 leads and beyond (up to 200). The smaller CSPs hold discrete devices and high-performance analog (including mixed-signal and RF) functions, while the mid-range CSPs are used for ASSPs and other subsystem chips. The highest-lead-count CSPs serve SoCs.

CSPs have very low parasitics. Their lack of actual leads gives CSPs very low series inductance (ESL), making them ideal for housing RF and broadband communications ICs. A CSP's very low series resistance (ESR) is a byproduct of truncated leads, benefiting power discrete and integrated MOSFETs. A leadframe CSP also has a superior thermal conduction path to the pc board thanks to its exposed bottom copper leadframe. Furthermore, a CSP gets you to market faster. It incorporates analog, mixed-signal, and RF functions economically, both from a board space and a cost perspective. Unlike big SoC packages, CSPs don't consume lots of board overhead.

One myth is that CSPs are hard to handle in manufacturing. The vast majority of CSPs are handled by ordinary pick-and-place equipment without special considerations. The smallest waferscale CSPs are less than 1 mm on a side. These have masses so low that simply keeping them in place following the pick isn't straightforward. This is a solvable problem, though, and a small price for a package that's the size of a fleck of pepper.

There also is the myth that CSPs are hard to solder be-cause most of them have a 0.5-mm lead pitch. Fortunately, everyone agrees that the industry is heading to 0.5 mm. Modern equipment can deal with this once properly adjusted. There just isn't much margin for error. Packages without solder balls need a well-controlled volume of solder printed on board. It all boils down to controlling thickness a little better than the loose tolerances permissible.

Another myth is that CSPs aren't reliable. The fact is, manufacturers subject these packages to the same reliability criteria applied to all semiconductor packaging. Perhaps a bad apple exists among the many CSP variants, but even wafer-scale CSPs perform very well thanks to proprietary die coats and pliable solder balls (e.g., National's microSMD). Underfill is only necessary for the largest CSPs.

OEMs and contract assemblers must increase the CSP learning curve. Let's embrace this exciting new technology now.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.