Co-Emulation Rides Standard To New Heights

When it comes to systems on a chip (SoCs), you can't build what you can't verify. With ingredients like multiple processors and DSPs, other IP blocks including memory and I/O, as well as custom logic all in the mix, verification stands as the tallest hurdle between SoC design and tapeout.

Software simulators ran out of gas long ago in the SoC realm. They've been aided, though, by the emergence of transaction-based verification, a technique in which large amounts of data representing single or multiple clock cycles can be passed into simulation without multiple calls. Most hardware-verification languages, such as Vera and e, are event-based and must provide data every clock cycle or even every subcycle. Transactions, on the other hand, address architecturally visible data types. An Ethernet transaction deals with an entire Ethernet packet, while a PCI DMA bus transaction deals with an entire burst transfer.

Yet, even transaction-based simulation methods have been overwhelmed by the complexity of 20-million-gate SoCs. Emulation and hardware-accelerated simulation have filled the gap to some degree, but they're still not enough.

Now emulation has been linked with transactions through a partnership between Aptix Corp. and Zaiq Technologies in Aptix's SoC Validation Lab, a transaction-level co-emulation environment that offers numerous benefits (see the figure). These include a seamless migration from simulation to co-emulation and reusability of testbenches from block to system level—and, of course, lots of speed and capacity.

Both Aptix and Zaiq bring key proprietary technologies to the fore in the SoC Validation Lab. Aptix comes on board with its Expeditor (formerly known as the Module Verification Platform), a co-emulation software/hardware system. It includes optional interfaces for most major VHDL and Verilog simulators, as well as a C-language interface.

Zaiq contributes its Systemware Verification Components (SVCs). The growing library, which includes 10/100 Ethernet, Gigabit Ethernet, SPI-4.2, SPI-5, PCI, PCI-X, Packet over SONET, USB 2.0, and ARM AMBA 2.0, provides the software macros that bridge the transaction level of abstraction to actual pin- and cycle-accurate signals. For example, an Ethernet SVC might deal with an Ethernet packet and interpacket gap as a single transaction on its software interface but expands this into thousands of clock cycles of serial data on its hardware interface.

Together, the companies put in place the final piece of the puzzle that makes it possible to use transactions in co-emulation—the first independent implementation of Accellera's new Standard Co-Emulation API: Modeling Interface (SCE-API: MI) standard since Accellera approved it in May. The Aptix/Zaiq implementation of the SCE-API standard is also the first in a rapid-prototyping environment as opposed to a pure emulation environment. That carries broad implications for the potential transportability of transactor models between pure emulation systems, such as Mentor Graphics' V Station, and Aptix's Expeditor co-emulation system (see "About The SCE-API," p. 48).

Transactions provide three main benefits. The first is for test writers, who now can remain in the transaction domain when writing tests for, say, Ethernet packets. They needn't concern themselves with lower-level details of bus protocols, address and data lines, or bus acknowledgements.

The second benefit is the reusability of the testbench. Tests written at the system level with C/C++ models can be reused with the simulator and also with the emulator by changing the underlying bus-functional model (BFM).

But the real key to transactions is how they bolster performance. The transaction-based transport layer, embodied in the Aptix/Zaiq-codeveloped SCE-MI Transporter, maps transaction requests from the C side into HDL registers that control the BFM state machines.

Using a transaction transport layer brings a substantial speed advantage over sending cycle-by-cycle or individual signal PLI requests. When compared with simulation, speed can jump from 600× to over 4100×. Capacity can reach up to 10 million gates.

Thanks to the SCE-API, the Expeditor takes the ease of use for both simulation and emulation up several notches for the end user. To the user, emulation looks the same as if it were simulation, only running many, many times faster.

Another Zaiq contribution to the SoC Validation Lab is the PREP Messenger transaction-level verification environment. It includes interfaces from C, C++, and/or SystemC to most of the popular VHDL and Verilog simulators. This facilitates stimulation of the device under test (DUT). PREP is a test writing and control module that assembles the Systemware SVCs and any customer-created transactors for feeding to the transport layer.

That transport layer, also contributed by Zaiq, is called TestBenchPlus. This layer supports multithreaded operation so that concurrent tasks can be initiated. The result is more rigorous testing of the DUT running on the Expeditor, which more closely simulates real-world system-level performance.

Also from Zaiq is an application-specific Platform Library and environmental tools that facilitate data generation and checking for serial protocols. In addition, the library provides configuration management for regressions, performance monitoring and control functions, and graphical and command-line user interfaces.

List pricing starts at $75,000, which includes the PREP Messenger, TestBenchPlus, the SCE-MI Transporter and a selection of Systemware verification IP. This price does not include the Expeditor. That unit, plus at least one Prototyping Module, is required to complete the SoC Validation Lab. All are available now.