Electronic Design

Comm Processor Offloads Host, Delivers Gigabit Data Streams

Leveraging dual Gigabit/s Ethernet ports, an 833-MHz CPU, and many other enhancements, this comm processor lets systems add more features.

As data transfer rates increase and system integrators strive to bring more services and features to the communications systems they're crafting, current-generation communications processors are running out of steam. Future enterprise routers, media gateways, wireless basestations, and multiservice access platforms must offer new services, greater flexibility in their system configurations, and an overall lower price per port.

To meet these system needs, designers at Motorola have developed their fifth-generation series of communications processors, the PowerQUICC III family. The first family member, the MPC8560, provides a highly integrated solution that gives designers dual triple-speed Ethernet ports capable of 10/100/1000-Mbit/s data rates and layer 2 acceleration. It employs a high-speed 32-bit PowerPC CPU based on the e500 core, which can operate at 600- to 833-MHz and higher clock speeds. It also has an enhanced communications processor module (CPM) that runs at 333 MHz, or about 50% faster than the previous-generation CPM on the PowerQUICC II processors (see the figure).

The processor actually packs many more enhancements and features. For example, to improve system expandability, designers equipped the PowerQUICC with a RapidI/O interface, a 64-bit PCI bus controller, and a 333-MHz double-data-rate DRAM controller. The low-pin-count 8-bit Rapid-I/O interface employs LVDS signaling and allows data transfers to take place between two chips at a peak data rate of 8 Gbits/s in each direction. Multichip systems can also be implemented by using RapidI/O bus switches.

Besides adding these new features, designers maintained backwards CPM software compatibility. That allows systems built with the previous-generation PowerQUICC II chips to be upgraded without massive software updates.

In comparison to the forthcoming MPC8560, most of today's integrated silicon solutions are too slow to handle the gigabit data streams and the complex control/analysis tasks required on those high-speed streams. Or else, they don't provide the level of integration to deliver a cost-effective system solution.

To match the PowerQUICC III's level of functionality, today's system designers would have to use discrete building blocks—an 833-MHz RISC CPU, multiple Gigabit Ethernet interfaces, specialized communications blocks for handling ATM and TDM interfaces, and much more. Such a discrete solution would occupy significantly more board space, consume much more power, and take lots of custom software to make all the blocks play together.

Integrating all key building blocks on one MPC8560 provides a system-on-a-chip solution that can scale with the performance needs of systems for many years. Simultaneously, the design permits future extensions through an on-chip, nonblocking, crossbar connection fabric called OCeaN (On-Chip Network). This fabric offers a 22-Gbit/s per-port peak bandwidth in each direction in addition to independent transaction queuing and flow control.

A dual-issue superscalar CPU, the high-performance e500 processor core achieves a throughput of 1850 MIPS when clocked at 800 MHz. This high-throughput processor enables the PowerQUICC III to handle many functions that previously required the host CPU, potentially eliminating the need for a host CPU. By shifting the forwarding plane processing to the CPM, designers can also unburden the e500 core, leaving it free to perform higher-level system functions.

The processor core contains a seven-stage pipeline and 32 kbytes each of eight-way set-associative cache for instructions and data, and a 256-kbyte level 2 cache. The second-level cache can also serve as either one 256-kbyte memory-mapped SRAM block or can be split into 128 kbytes of L2 cache and 128 kbytes of SRAM. The core offers plenty of compute performance for the control-plane functions. It also supplies the horsepower to run the software that implements the many value-added services system users want in such systems as enterprise routers, multiservice access platform trunk and line cards, media gateways, and wireless basestations.

In addition to the faster PowerPC processor core, designers revved up the PowerQUICC's communications processor module (CPM) so it can deliver more than 1 Gbit/s of aggregate communications bandwidth. The CPM block packs its own RISC processor, 32 kbytes of dual-port RAM, 128 kbytes of ROM, and 32 kbytes of information RAM to hold the protocol microcode. These memory blocks are significantly larger than the memories included on the PowerQUICC II series. This permits the new processors to handle more-complex protocols, updates to existing protocols, or custom protocols.

Moreover, the module includes two UTOPIA Level II master/slave ports that have multi-PHY support, three 10/100 Ethernet media-independent interfaces, eight time-division multiplexed interfaces (supporting two groups of four TDM channels), and capability for T1, CEPT, T1/E1, T3/E3, PCM highways, ISDN basic rate, ISDN primary rate, Motorola's own interchip digital link, and others. The module also features four HDLC serial links, three fast communications controllers (FCCs), two multichannel controllers (MCCs), four serial communication controllers, and eight transmission convergence layers between the TDM and fast communication channels.

The FCCs can support 155-Mbit/s ATM segmentation and reassembly (AAL0, 1, 2, 3/4, 5, TM 4.0 CBR, VBR, UBR, and ABR traffic types) and up to 64k external ATM connections. Further, the FCCs can deal with 10- or 100-Mbit Ethernet with CDMA/CS, and 45-Mbit/s HDLC/transparent (clear-channel) communications. Each MCC handles 128 serial full-duplex 64-kbit/s data channels and can be configured into four subgroups of 32 channels each. With both MCCs active, the chip delivers 256 full-duplex TDM channels.

Designers at Motorola made certain that data could move with no obstructions from block to block and from block to I/O port. To do that, the chip uses the OCeaN switch fabric and a special coherency module that helps manage coherent and noncoherent data traffic. The module eliminates unnecessary traffic on the processor bus by forwarding transactions to the processor bus only if coherency checking is required.

The module can concurrently process up to three coherent transactions interleaved with three noncoherent transactions as they flow through a pipeline of snooping, target mapping, and target buffer availability checking. Because serialization isn't required for noncoherent I/O traffic, the OCeaN fabric allows much higher levels of transaction concurrency. Thus, an OCeaN port can communicate with any other port in a full-duplex mode. That allows much higher transaction concurrency.

Because the PowerQUICC III family maintains CPM software compatibility with previous-generation devices, many tools and software developed for past processors can be used to develop new software. Additional software tools and operating systems will be available from Motorola and partner companies.

Price & Availability
Samples of the MPC8560 PowerQUICC III communications processor will be available in the first half of 2003. However, as the processor is software compatible with the previous-generation PowerQUICC II, the bulk of software development can take place via current-family devices. The mid-range MPC8560 costs $125 each in 10,000-unit lots.

Motorola Inc., 6501 William Cannon Dr. West, Austin, TX 78735; Nishin Sura, [email protected]; www.motorola.com.

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