The Puma AEL1006 can drive vertical-cavity surface-emitting laser (VCSEL) diodes while providing 10-Gbit/s physical-layer (PHY) support. Implemented in a 130-nm CMOS process, it also simplifies next-generation serializer/deserializer (SERDES) systems. The chip's clock synthesizer allows Ethernet/XAUI clock rates to be generated from a low-cost 50-MHz clock input, further reducing the cost of optical modules employing the AEL1006. The Puma AEL1004 10-Gbit PHY offers onchip clock synthesizers that eliminate the need for board designers to provide two clock sources for Ethernet and Sonet/synchronous digital hierarchy (SDH) timing requirements. With the company's scheme, a single clock input of 155.52 MHz will drive either the Sonet/SDH or Ethernet/XAUI timing requirements. On-chip cleanup circuits also permit the chip to deliver stratum-3 level line-timing capability for Sonet/SDH timing requirements. Contact the company for volume pricing.