Electronic Design

Components/ Interconnects/ Packaging: Interconnects & Packaging

Consumer Market Challenges Packaging And Interconnects

To a large extent, the consumer sector will dictate the trends in packaging and interconnection technology developments. Digital cameras with paper-thin flash-memory cards, smart cards the size of business cards that carry tons of personal information in a person's wallet, and robotic toys with electronic smarts crammed into tiny crevices are just some of the huge influx of applications pushing the envelope. Not only will performance be important, but the cost factor will be huge. Thus, packaging and interconnect designers must come up with robust solutions at the lowest possible cost.

A sizable hurdle will be how to solve capacitance, ringing, overshoot, and other effects in interconnect systems as signal speeds rocket to tens of gigabits/s, while suppressing costs by using improved processing technologies. Here, it would be preferable to work with standard pc-board materials like FR-4 and copper interconnects—two mature technologies. Last year, for example, Tyco Electronics (www.tyco.com), along with IC manufacturer Gennum (www.gennum.com), demonstrated that FR-4 material can indeed be improved with better processing. They showed that Tyco's Z-Pack HM-Zd connector and a pc board working with a Gennum chip can handle serial data at 10 Gbits/s for up to 22 in. of copper using FR-4 material.

As chip densities increase, so will the need to reduce on-chip signal delays. One promising method, devised by researchers at Johns Hopkins University (www.jhu.edu), involves a hybrid integration approach that implements silicon on a synthetic sapphire substrate, instead of conventional bulk silicon CMOS. It promises to speed up on-chip signal transmissions by 100-fold and reduce power consumption, as sapphire is an insulator.

Ceramics will continue to play a large role in packaging technology. Low-temperature cofired ceramic-on-metal (LTCC-M) substrates will improve thermal conductivity, featuring lower shrinkages in the x-y plane. A competitive trend is to use multilayer pc boards on BGA platforms for lower cost.

The move to more leadfree packages (no lead, pb) will accelerate. While there's no consensus yet on this issue, a clearer picture should emerge soon.

>MORE STANDARDS WILL EVOLVE, like the HSBI (High-Speed Serial Backplane Initiative), to facilitate the application of high-speed serial links capable of multigigabit per second data rates over backplanes at longer distances. This will help designers of high-throughput systems merge connectors, sockets, backplanes, and pc boards, while maintaining signal performance.

>AS BACKPLANE AND CONNECTOR SIGNAL SPEEDS INCREASE, more and more reference design platform kits will be available to users to validate their designs. These kits will evolve from a combined effort of connector, IC, EDA software, and test-equipment vendors and will give users a means of accurately determining how their designs will fare under specific applications.

>3D PACKAGING WILL RAPIDLY move forward as advances in wafer thinning and handling, wirebonding, and materials allow more silicon in smaller footprints, conserving valuable pc-board space, shortening chip-to-chip routing interconnections, and preserving signal integrity. Moving beyond popular memory-stacking applications, 3D packaging will include logic and analog IC applications.

>MULTICHIP MODULES (MCMs) and LCCs will eventually shift to chip-scale packages (CSPs) in some applications like power supplies, where they'll serve as system-level building blocks. While MCM and LCC designs continue to flourish for power-supply and RF and microwave designs, CSPs, which can presently handle up to 25 A of current, are well suited for portable applications.

>EXPECT PROCESS IMPROVEMENTS to reduce costs of high-pin-count packages. One notable example is a fine-pitch technique that was developed by Advanced Interconnect Technologies (www.advanc-edinterconnect.com). It merges the high-density benefits of fine-pitch ball-grid arrays and the low-cost advantages of quad flat packs (QFPs). The product uses I/O pads on the bottom to replace the traditional gull-wing leads. The die attaches to the leadframe using either wirebonds (a) or copper pillar bumps (b). See associated figure.

>VERY STABLE AND HIGH-THERMAL CONDUCTANCE low-temperature ceramics (LTCCs) are on the horizon, important for burgeoning RF and optical applications. Work by Lamina Ceramics (www.laminaceramics.com) is just one indication of this trend. Its low-temperature cofired ceramic-on-metal LTCC-M process decreases x-y-plane shrinkage to about 0.1%, compared with the 12.7% to 15% shown by LTCC and HTCC processes. It also improves thermal conductivity and promises to reduce component sizes and costs. See associated figure.

>THE CONNECTOR INDUSTRY must come up with improved FR-4 pc-board materials to extend the material's life and improve copper transmission paths for increased signal performance. Adaptive and pre-emphasis equalization techniques and counter-boring plated through-hole vias for reduced capacitance effects will go a long way to solving these problems, as will new connector technology.

>DEMAND FOR higher-density fine-pitch connectors will push pitch (center-to-center) spacings below the present 0.3 mm to under 0.1 mm, stretching connector stamping and molding manufacturing methods to their limits. Flexible pc manufacturers will also be challenged to deliver products that can satisfactorily mate with newer connectors at very tight tolerances.

>CONNECTOR MANUFACTURERS will work even closer with IC manufacturers to ensure satisfactory connector performance, as data rates increase to 10 Gbits/s and higher over backplanes, pc boards, and transceivers.

>CONSUMER APPLICATIONS will make an enormous impact on packaging and interconnect technologies, particularly when it comes to low cost. One example of the shape of packages to come is the Micro-Package developed by Silicon Storage Technology (www.sst.com) for space-sensitive applications like Bluetooth modules and mobile devices. With the industry's thinnest flash-memory package height of 0.52-mm maximum in a 4- by 6-mm footprint, it's an easier-to-use, smaller-size alternative to BGA, bare-die, and other options.

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