High-speed DSP system designs are becoming increasingly complex due to the DSP's clock speed and potential issues related to signal integrity, power distribution, noise, and electromagnetic radiation.
For these reasons, designers need to understand the importance of the minimum current-return loops and other high-speed phenomena. They must also apply good high-speed design practices to reduce these effects before it's too late. And, future DSP architectures will include wider data buses with more simultaneous switching. This increase will lead to even more transients on DSP power-supply pins, making it critical for engineers to learn how to deal with such problems.
To combat the potential noise, one needs to understand possible sources and their consequences. Today's high-end DSPs have clocks running at 1 GHz, and they send signals through I/O pins at rates approaching 500 MHz.
Fast switching signals lead to considerable harmonics, and pc-board traces can act as antennas. Noise degrades audio, video, graphics, and communications performance. When radiated through traces, noise can hinder getting a system FCC certification or a CE mark.
Some sinister effects arising from fast clocking and switching aren't immediately obvious. When powering up a high-speed DSP to a known state, the voltage regulator must be able to supply an inrush current as large as 1.5 A. Too much inrush current can send a voltage regulator into thermal or overcurrent shutdown, so choose one accordingly.
Due to poor regulation, supply-voltage fluctuations can also lead to random logic failures. To inhibit droop on the output of linear regulators, you normally add a capacitor. A large value can supply plenty of current during fast switching. But be careful, because linear regulators can handle only a certain amount of capacitance before they go into oscillation and create noise.
Board traces from the regulator to the DSP have an inductance. Yet even with good decoupling capacitors, a charge needs time to reach the proper level. The DSP's switching can load down the voltage regulator, and the resulting voltage droop can again lead to random logic failures. Even worse, random failures are hard to isolate and debug because designers must guess which board section might be at fault.
BACK TO THE SOURCE
Today's sophisticated systems have more potential sources of noise than ever. One particularly important source that involves crosstalk is often neglected. In high-speed systems, signal ground paths are determined by the frequency of operation. In fact, a signal trace's ground return path can vary widely based on frequency. For low-speed signals (typically below 10 MHz), signals exit from the source into the load and return to the source on the ground path with least resistance, meaning the shortest path.
Things get trickier with signals above 10 MHz. Here, the current returns on a ground path with the least inductance, which means the smallest loop area. The return on the ground plane follows a path underneath the signal trace, which generally isn't the most direct or shortest path. The return signal then spreads out with a current distribution (Fig. 1). So the return paths of adjacent signals can easily overlap, leading to crosstalk.
Several techniques help minimize crosstalk, including trace spacing. While many engineers feel that setting them one trace-width apart is adequate, it's better to double that spacing on high-speed DSP systems to reduce return-loop overlap. (For differential signals, such as those on Ethernet or USB, follow spacing guidelines that lead to the signal pair with the required matched impedance.)
Remember that doubling the space between signals reduces crosstalk by a factor of four. Second, provide shielding for critical signals, like clocks, by routing them on an inner layer between the power and ground planes. If this isn't possible, an image plane (ground plane) can be used on the layer immediately below those critical signals.
When reworking a board and adding a signal wire, designers need to add a ground wire in parallel with it. This supplies a high-speed current return path and makes for the smallest area in the current loop. Without this extra path, the return current's path might create large loops and pick up noise.
When combating crosstalk, remember that fast edges create more harmonic energy, and thus, interference. Energy from odd harmonics dominates a signal with a 50% duty cycle, often the case with clocks and other DSP signals. An effective way to reduce this harmonic content is by slowing the rise time (TR). Doing so moves the curve of noise amplitude toward lower frequencies, which better attenuates harmonic components (Fig. 2). One method for modifying rise times adds series-termination resistors on traces. But sometimes, rise or fall times can't be manipulated due to timing margins like setup/hold times.
Terminating lines also reduces transmission-line reflections and ringing. Determining if a trace acts as a transmission line is accomplished when the rise time is less than twice the propagation delay (TP) in the line (that is, when TR < 2TP). For an FR4 type of pc-board material, TP is on the order of 1 ns for a 6-in. trace, and TR for today's high-speed DSP signals is about 1 ns. Clearly, it's smart to keep traces as short as possible. If a trace must be long enough to act as a transmission line, the designers must use proper trace-termination techniques like series termination (a resistor in line with the output driver) or parallel termination (a resistor to ground at the load). In doing so, a resistor should be selected that matches the trace's pc-board characteristic impedance to minimize the reflections.
ANALOG AND DIGITAL PLLs
Another area of concern for noise is phase-locked loops (PLLs), which DSPs integrate in growing numbers. In fact, some DSPs use both analog and digital versions (Fig. 3). The analog PLL, implemented with an analog filter, finds use in applications that require low jitter, like a USB port. But it takes more silicon to implement this type because analog filters typically need large capacitors. The digital PLL requires no capacitors, making it smaller and with lower leakage current, which is useful in applications that require fast wakeup time and low power, such as cell phones. Yet it's more sensitive to power-supply noise and input jitter.
When isolating a power supply feeding a PLL, a pi filter does a good job on high-frequency noise. But it's poor at removing low-frequency noise in the range below 1 MHz, unless a multistage filter network is employed. These networks, though, can be troublesome in fast switching circuits because of the critical layout of their many discrete components. In these cases, it's better to use a low-dropout (LDO) regulator, because these devices are designed to have a high power-supply rejection ratio (PSRR) at low frequencies. Selecting a high-PSRR regulator is important if the design runs in a noisy environment with considerable low-frequency transients. Automotive electronics and other electrical/mechanical devices are good examples.
Engineers should also watch out for another area involving both analog and digital circuits. Most designers tend to keep analog and digital grounds separate so digital noise doesn't creep into analog sections. For low-speed circuits, it's permissible to isolate them. But for high-speed circuits, like those in video sections, separate grounds should be avoided. Recall that fast switching currents try to find the smallest current loop. So when an isolated ground system won't allow them to find this path, they locate an alternate path to the source. This ultimately leads to a potential difference, current flow, and radiation.
Consequently, it's advisable to short the analog and digital grounds together to provide a direct path. When doing so, try to short the grounds at the entry point of the digital data, such as where a DSP feeds signals to a digital-to-analog converter. This short won't upset the low-frequency signals. The signals will ignore this shorted path because they seek the physically shortest return route to the source.
NO ONE BEST VALUE FOR DECOUPLING
Another effective weapon against noise consists of the judicious application of capacitors. Decoupling capacitors supply a low-impedance path to ground to shunt unwanted high-frequency energy, while bulk capacitors shunt low frequencies to ground and also provide local charge storage for decoupling capacitors.
What is the optimum value for a decoupling capacitor? There's no best value because of counteracting effects. A capacitor's impedance drops with frequency and capacitance, except when its parasitic inductance comes into play. A capacitor has a resonant frequency of:
As signal frequencies exceed the resonant frequency, the capacitor becomes inductive and no longer effectively filters them.
Even though a high-value capacitor gives a low impedance and more charge storage to reduce droop, its lower resonant frequency makes it a poor choice for high-frequency signals. On the other hand, a smaller value neither supplies much charge current nor filters low frequencies well. If possible, two capacitors should be used--one small and one large--on the power-supply ground. Or if that's not practical, a good compromise value is 0.01 µF. Bulk capacitors should be relatively large, and a good design rule states they should combine to at least 10 times the total decoupling capacitance in a given region.
Also, be aware of different properties for various capacitor types. At 100 kHz, a 100-µF electrolytic has an equivalent series resistance (ESR) of roughly 0.6 Ω. On the other hand, the same value tantalum drops ESR to roughly 0.12 Ω, making them preferable for bulk capacitors. Next, consider decoupling capacitors. At 1 MHz, a 1.0-µF polyester capacitor has an ESR of approximately 0.11 Ω, while a 0.1-µF ceramic specifies roughly 0.12 Ω at that same frequency. Thus, ceramic capacitors are preferable for decoupling.
TIPS FOR PLACING CAPACITORS
When positioning decoupling capacitors around a high-speed DSP, follow a few rules of thumb. First, place a decoupling capacitor on every power pin, or at least as many as possible around the device. When placing them, examine the DSP's circuitry. Some sections hold the DSP core; another might hold high-speed circuitry such as a memory interface or digital PLL; another section might hold an analog PLL. To effectively decouple such a complex DSP, draw two imaginary lines from opposite corners to create an X. Once this is complete, analyze each of the four regions separately.
Consider an OMAP5910 DSP and the region that contains a digital PLL and an external memory interface (Fig. 4, left region). The datasheet specifies a peak core-current consumption of 170 mA. The device has a total of 13 core-voltage pins. So, each averages 13 mA. The three core-voltage pins in the region with the digital PLL and external memory interface draw 39 mA. To ensure accuracy, add a 100% margin leading to 78 mA.
Next, estimate the peak I/O current, assuming all 54 I/O lines switch 4 mA (a value on the device's datasheet). Multiply 4 mA by the number of I/O pins for the region. This conservative approach assumes all I/Os switch simultaneously, leading to 216 mA going through the eight I/O voltage pins in this region.
Because the core and I/O voltages operate at different frequencies, supplies must be decoupled using the correctly sized capacitor. Use C = I(dV/dt), where I is the peak current just calculated, dV is the maximum allowable ripple voltage (assume 10 mV), and dt is the risetime (assume 1 ns, typical of the OMAP5910). For the core capacitance, C = 78 mA × (1 ns/10 mV) = 0.0078 µF. For the 216-mA I/O current, the capacitance equals 0.022 µF.
It's desirable to have a capacitor for each core power pin, but the pc board offers only limited space. For the OMAP5910 BGA package, there's enough space for four capacitors per region. So to decouple the core voltage pins, select two capacitors with a total value of 0.0078 µF. Arrange two 0.0047-µF ceramics for the shortest distance from the pins to ground.
Switching frequencies also come into play. This section of the core switches at 150 MHz, while its eight I/O pins switch at 75 MHz. Look at capacitor datasheets to find one whose parasitic inductance leads to a self-resonant frequency above 150 MHz. Use the other two capacitor positions to decouple the I/O-voltage pins. To get a total value of 0.022 µF, pick two 0.01-µF ceramics with a self-resonant frequency above 75 MHz.
Next, turn to the bulk capacitors. As noted, a good rule is to select the total bulk capacitance to be at least 10 times the total decoupling capacitance. In this example, the DSP's total core-voltage current is 338 mA. Using the formula given earlier leads to 0.0338 µF, and multiplying by 10 gives roughly 0.39 µF.
Apply the same procedure for the I/O voltage, and you get a capacitance of 0.84 µF. Summing the values brings 1.23 µF. The best technique is to add one bulk capacitor to each region. Dividing 1.23 µF by four then gives 0.3075 µF. Multiply that value by 10 to arrive at 3.075 µF.
The smallest bulk-capacitance value available as a surface-mount device is 4.7 µF, which works fine. Select tantalum bulk capacitors, if possible, or else a surface-mount electrolytic. An evaluation of the four regions in this fashion leads to the values shown in Figure 4.
When placing the decoupling capacitors, put them on the bottom of the pc board next to the device pins. It's also a good idea to alternate between the core and the I/O values to minimize the distance from any lead to its capacitor. To get the bulk capacitors close to the decoupling capacitors, put them on the top of the board. This positioning minimizes traces, and thus current loops, while also reducing radiation and parasitic inductance.