Increasingly demanding signal-processing tasks steadily take the steam out of the compute resources on commodity DSP chips and high-performance general-purpose CPUs. Complex math operations, such as those needed in wireless communications, medical imaging, and machine vision applications, can easily consume billions of MACs.
The FastMATH processor, a single-chip solution from Intrinsity Inc., makes short work of the computations by combining a 2-GHz MIPS32 RISC processor with a vector and math coprocessor to deliver a throughput of over 64 Goperations/s (see the figure). The novel vector and math computational block's 4-by-4 array of 16 math-optimized processors lets the chip run rings around potential competition.
Each math-optimized processor in the array can execute 16 complex MAC operations every four cycles using a 2-GHz clock. That gives the entire array a computational throughput of 8 × 109 MACs per second. Each math processor contains a local 16-word by 32-bit register file (also configurable as a 32-word by 16-bit file), a 16-bit multiplier and adder, and dual 40-bit accumulators to hold the complex results.
The aggregate throughput enables a single FastMATH chip to execute more than 550,000 1024-point radix-4 fast-Fourier transforms/s. Such performance is more than five times better than top of the line DSPs and AltiVEC PowerPC processors. To ease the data-transfer overhead requirements, designers incorporated a 1-Mbyte level 2 cache on the chip that's accessed by both the math array and the RISC core, which also includes 16-kbyte level 1 caches for the data and instruction streams. A pair of RapidIO ports on the FastMATH processor chip provides high-speed channels for intrachip communications and delivers a 32-Gbit/s throughput.
The initial FastMATH processor version will be rather power-hungry, consuming about 13.5 W when operating from a 1-V power supply and running at 2 GHz. Also available is the FastMATH-LP, which consumes about 5 W and delivers about half the throughput of the FastMath.
For applications that don't require the high-speed math, the FastMIPS version eliminates the vector and math coprocessor. Intrinsity calls this MIPS32 processor chip the fastest MIPS-compatible CPU available and says that it's the first MIPS-based chip to include a pair of RapidIO ports. Powered by a 1-V supply, it consumes about 8 W.
A development board and an extensive tool suite of both MIPS development tools, several third-party development tools, and a company-developed signal-processing library of basic compute functions support the processors. Samples of the FastMIPS and FastMATH processors are available. Samples of the low-power FastMATH chip will be ready in the fourth quarter. Pricing in 10,000-unit quantities runs from $99 for a 1.5-GHz FastMIPS chip to $349 for the 2-GHz FastMATH chip. A faster version slated for 2004 will clock at over 3 GHz.
Intrinsity Inc. • www.intrinsity.com