Electronic Design

Custom SoC Strategy Shaves Off Up To One Year Of Development Time

One of the most vexing elements of SoC development cycles is hardware/software co-development, which often starts too late and with the project on the line. Toshiba's SoCMosaic custom-chip co-development strategy reduces software-development time by up to one year.

The strategy builds on Toshiba's SoCMosaic program for IP-rich custom SoCs. Key to it is WhiteEagle Systems' Swordfish FPGA emulation system and Mentor Graphics' Seamless version 5 co-verification tool. The former is a hardware box with an expandable emulation engine and a wide-bandwidth host interface. With the latter, software and hardware development can be parallel activities.

Helping to ensure working first silicon, the environment provides a front panel that lets software developers work with different SoC simulation modes. Programmers use the SoCMosaic Platform Support Package (PSP) to develop their code, which is independent of the simulation mode. The code can be migrated seamlessly to any supported run-time environment, including functional model, mixed functional/gate model, FPGA, an optional development board, and the custom SoC. The PSP also provides a consistent run-time environment for C code.

The environment supports a broad range of programming and debugging tools. The roadmap projects rollouts of system-level architectural simulation; a debug environment; high-level C models for pre-implementation functional work; and tools for area, power, and speed optimization.

The development environment is available now to SoCMosaic customers. Pricing consists of tool licensing and engineering fees that vary with project complexity.

Toshiba America Electronic Components Inc.
[email protected]
www.toshiba.com/taec/

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