Addressing a variety of peripheral applications including printers, fax machines, digital-photo frames, and VoIP equipment, the latest member of the SPEAr family of configurable SoCs is the company's first 65-nm process technology device in the family. Transfer of the SPEAr family to 65-nm process technology promises higher density, better performance, and power-reduction features. The configurable SoC integrates an ARM926EJ-S processor core running at 333 MHz with two16k memory caches and up to 300K gates of embedded configurable logic. It integrates interfaces supporting LP-DDR and DDR2 memory, a Fast-IrDA interface, Ethernet MAC, three USB2.0 ports, UART, SPI, I2C, up to 102 programmable GPIOs, and a total of 72 KB of SRAM and 32 KB of boot ROM. For printing applications, the device includes a set of image-pipeline accelerators, rotation engine, JPEG codec, LCD controller, and a SDIO/MM card interface. Additional features include a 10-bit ADC, crypto accelerator based on proprietary C3 IP, static memory controller, TDM and SLIC controllers, and a camera interface. The device supports most operating systems including Linux, VxWorks, ThreadX, and Windows CE and comes with an evaluation board. Sampling now with volume production set for the end of the third quarter, price for the SPEAr Basic is $6 each/20,000. STMICROELECTRONICS, Lexington, MA. (888) 787-3550.
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