Electronic Design

DAC Preview: Verification

The topic of verification is a perennial hot potato at DAC. Given its status as chief time/resource sink in the overall design cycle, verification and improvements in the process thereof will be of keen interest throughout the 44th DAC.

Real Intent will focus on two new products in its formal verification portfolio, and will also unveil two upgraded products.

Meridian, one of the two new offerings, is a next-generation clock-domain-crossing (CDC) product that verifies the correctness of data crossing clock domains in digital designs. The key differentiators for Meridian are that it’s able to validate not just the structure of the crossing circuitry, but also its functionality. It does this through the use of formal analysis. A major benefit of formal analysis is that the reports are more succinct, so the requirements for manual sign-off are drastically reduced. Meridian, available now, costs $60,000. It replaces Real Intent’s earlier product, Clock Intent Verification.

Another new product, EnVision TCV (Timing Constraint Verification), verifies all timing constraints, whether they’re used for clock crossings or for functional reasons. It combines Meridian and Real Intent’s PureTime software to prove the correctness of all paths with exceptions. It’s available now for a limited time at a promotional price of $100,000.

The latest release of PureTime (v2.0) builds in features including SDC (Synopsys Design Constraints) exception linting. The enhanced tool verifies exceptions, which are placed on clock crossings. PureTime, available now, is priced at $95,000.

Replacing Real Intent’s earlier product called Implied Intent Verification, Ascent is an automatic formal-verification product. It offers higher completion rates for checks, and allows users to control the circuit through use of System Verilog Assertions (SVAs) or Property Specification Language (PSL) constraints. Ascent is available now and priced at $34,500.

Agilent EEsof EDA will demonstrate what it’s terming a breakthrough in high-frequency Spice simulation for high-speed digital board designers. These improvements are built into an upgrade of the company’s Signal Integrity Designer suites, which start at about $25,000.

Jasper Design Automation will come to DAC with two product releases announced earlier this year. The first is v4.3 of the company’s flagship product, the JasperGold Verification System; the second is v1.1 of the GamePlan Verification Planner.

In JasperGold Verification System v4.3, users will find an Express option with easier formal-verification setup and faster results. A new parallel engine supports multithreaded architectures while providing strong support for formal assertion languages. The tool also enables reuse of properties from your simulation environment without need for recoding.

For verification planning, v1.1 of GamePlan lets users generate and track a structured verification test plan. It identifies which features of a design need to be tested, as well as the technologies that testing will require. It prioritizes design features and their corresponding tests. The tool provides a method for tracking and reviewing overall verification progress and integrates multiple verification technologies into a single, consistent overall plan.

GamePlan v1.1 is available freely for download at www.jasper-da.com/gameplan.

Tanner EDA, one of the industry’s longest-lived vendors, will be at DAC to show off the new multithreading simulation capability of its T-Spice simulator for analog and mixed-signal chip designs. This capability has been developed for use on computers with multiple processor cores. On average, the enhanced tool is said to deliver 40% faster simulations on single-processor, dual-core computers and 80% faster run times on two-processor, dual-core machines.

The simulator is tightly integrated with schematic capture and waveform viewing. Maximum benefit of the latest release is realized in simulation-intensive projects involving high performance or large device-count designs.

T-Spice generates fast and accurate simulations of analog and mixed-signal IC designs. It can read HSpice and P-Spice netlist formats directly and includes a simulation manager as well as device modeling features. T-Spice offers support for the latest industry models, including Penn State Philips Models (PSPs), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC, and MEXTRAM.

Multithreading will become a standard feature in the T-Spice simulator beginning June 2007. T-Spice starts at $6495 per seat.

Real Intent (DAC Booth #5260)

www.realintent.com

Agilent EEsof EDA (DAC Booth #6364)

eesof.tm.agilent.com/products/design_flows/signal_integrity

Jasper Design Automation (DAC Booth #2853)

www.jasper-da.com

Tanner EDA (DAC Booth #4873)

www.tannereda.com

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